v6 connector renumber (submodule b007c7c) + Copper Plan map

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt

03-Architecture-Hardware/2026-09-02_Drogheda_v6-Copper-Plan_Placement-EMC-Guide.html

@@ -63,7 +63,7 @@ a{color:var(--plane)}
 <h1>EinarBoard v6 Copper Plan</h1>
 <p class="sub">Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.</p>
 
-<div class="warn"><b>Before placing anything:</b> run <i>Update PCB from Schematic</i> once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit <code>ba70f62</code>), and the sync re-nets <code>P18</code>/<code>R126</code>/<code>C157</code> to a clean <code>/NTC2</code>. Tick <i>“delete footprints with no symbol”</i> in that dialog.</div>
+<div class="note"><b>Connector renumber (03-Sep, commit <code>b007c7c</code>):</b> P-refs now follow function order — <code>P1</code> 24V · <code>P2</code> 5V bench · <code>P3</code> battery (was P4) · <code>P4</code> fan (was P6) · <code>P5</code> cutoff (was P11) · <code>P6</code> reset (was P10) · <code>P7</code> NTC probe 1 (was P12) · <code>P8</code> NTC probe 2 (was P18) · <code>P9</code> panel LED (was P8) · <code>P10</code> RGB (was P14) · <code>P11</code> RS485 (was P15) · <code>P12</code> RS232 (was P16). ⚠ v5 field docs say "P12 = NTC" — in v6 that name is the RS232 port; update harness docs. The NTC2 net fix is applied and synced.</div>
 <div class="note"><b>Known leftovers from the auto-clustering:</b> ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — <code>L2</code>/<code>D2</code> (under U19's new outline), <code>L6</code>/<code>DB2</code>/<code>DB3</code>/<code>Q2</code>/<code>Dbk1</code> near U25, <code>C40</code>, <code>R40</code>/<code>R41</code> at Y3. Drag those few aside first and the board is clean.</div>
 
 <h2><span class="no">§0</span>Three laws that decide EMC at placement time</h2>
@@ -136,7 +136,7 @@ a{color:var(--plane)}
 <tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
 <tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>VEH5V input</td><td>at U6 input pins, after RS1</td></tr>
 <tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>MAIN5V output</td><td>at U6/Q7 output side</td></tr>
-<tr><td>C35</td><td>22 µF</td><td>BAT_PLUS</td><td>near P4; <code>/SW_BAT</code> ≥ 2 mm polygon, <code>/BAT_PLUS</code> ≥ 1.5 mm — the blackout path, a hard v6 requirement</td></tr>
+<tr><td>C35</td><td>22 µF</td><td>BAT_PLUS</td><td>near P3; <code>/SW_BAT</code> ≥ 2 mm polygon, <code>/BAT_PLUS</code> ≥ 1.5 mm — the blackout path, a hard v6 requirement</td></tr>
 </table></div>
 <div class="note"><b>RS1 (10 mΩ) is a Kelvin part:</b> the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.</div>
 
@@ -179,12 +179,12 @@ a{color:var(--plane)}
 <h2><span class="no">§7</span>The rest of the families</h2>
 <ul>
 <li><b>Ethernet</b> (<code>U11</code>/<code>U12</code>, <code>Y1</code>, <code>C90–C103</code>): one block, U11 close to J10 (magnetics are inside the HR911105A), crystal + 18 pF at the pins, the 3V3_ETH locals (<code>C92–C94</code>, <code>C98</code>, <code>C102</code>, <code>C103</code>) around U11. Keep the RJ45 pair region free of other routes.</li>
-<li><b>RS232</b> (<code>U15</code>): <code>C85–C88</code> are charge-pump flying caps — they carry the pump current, so they sit hard against U15; <code>C84</code> 100 nF at its supply pin. P16 at the edge.</li>
+<li><b>RS232</b> (<code>U15</code>): <code>C85–C88</code> are charge-pump flying caps — they carry the pump current, so they sit hard against U15; <code>C84</code> 100 nF at its supply pin. P12 (RS232 jack) at the edge.</li>
 <li><b>UART bridge</b> (<code>U10</code>, <code>Y2</code>, <code>C82</code>/<code>C83</code>): crystal caps at the pins, block near the MCU.</li>
 <li><b>Fan buck</b> (<code>U2</code>, <code>Cbst1</code>, <code>Ccomp1</code>, <code>C23</code>): a third switcher — treat like §4's loop, and park it in the noisy quarter near the power entry, away from GNSS.</li>
 <li><b>Accelerometer</b> (<code>U26</code>, <code>C158</code>/<code>C159</code> at VDD/VDDIO, <code>C160</code> bulk): ≤ 10 mm from a mounting hole, on stiff board — it should feel the chassis, not board flex.</li>
 <li><b>Rail sprinkles</b> (<code>Cu3</code> <code>Cu4</code> <code>C80</code> <code>C81</code> <code>C89</code> <code>C105+</code>…): every 100 nF on 3V3 pairs with one IC's power pin — when you move an IC, its 100 nF moves with it. <code>C118</code> 22 µF is the 3V3 bulk at the regulator.</li>
-<li><b>NTC channels</b>: pullup + filter (<code>R42</code>+<code>C24</code>, <code>R126</code>+<code>C157</code>) at the MCU; <code>P12</code>/<code>P18</code> jacks at the harness edge.</li>
+<li><b>NTC channels</b>: pullup + filter (<code>R42</code>+<code>C24</code> → P7, <code>R126</code>+<code>C157</code> → P8) at the MCU; <code>P7</code>/<code>P8</code> jacks at the harness edge.</li>
 </ul>
 
 <h2><span class="no">§8</span>Separation rules</h2>
@@ -207,5 +207,5 @@ a{color:var(--plane)}
 <li><b>Bench items carried forward:</b> measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.</li>
 </ol>
 
-<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026 to the clustered layout (commits <code>ba70f62</code> · <code>c7d2552</code>).</p>
+<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026: clustered layout + connector renumber (<code>c7d2552</code> · <code>43a967b</code> · <code>b007c7c</code>).</p>
 </div>

03-Architecture-Hardware/kicad

@@ -1 +1 @@
-Subproject commit 43a967b78e76f03840f14a9ebbe236fca4560040
+Subproject commit b007c7c1b10ccd86e49052852f392027c284f04d