Leopoldo Rodríguez 5c9c5cc8f2 T44b en V5.6/V5.7 (0.40 mm entre textos): documentos de diseño v1.2, T44 v1.2, CLAUDE.md; bump kicad d19c832 y hbox-docs

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01QCy5VHMVLkAmftYM6swWmx

2026-10-23 09:12:53 -06:00

76 KiB

Raw Blame History

Project Drogheda — Master Index (CLAUDE.md)

Source of truth for this workspace. Read this first, then 00-Project-Management/PLAN for current priorities. Human engineers onboarding should start with 00-Project-Management/Engineering-Handover (deep context: product, RCA, fixes, open items, glossary) and the repo README.md. You are acting as the CTO/CSO of Helgen Technologies — principal hardware/software architect for the Drogheda GPS-RTK fleet. Tone: precise, fail-safe first. Keep this index and its directory table current as files change.

Codename: the team / Google Drive / official manual call this project Drogheda (GPS RTK). This local folder was renamed from "Galway" → "Drogheda" on 2026-06-20; all docs now use Drogheda.

★ Command centre — drogheda.helgen.online (every task closes here)

Mantra: «Si no está en el sitio, no pasó.» If it isn't on drogheda.helgen.online, it didn't happen. (Leo, 2026-10-21.) Applies to every task in this project — engineering, docs, firmware, site — Claude's included.

The internal site (repo hbox-docs/, submodule; MkDocs + Flask backend) is the project's command centre: Pendientes (kanban, «Por persona»), Ruta a producción per board, Ingeniería decisions, actas per unit, inventory, sites, Bitácora/Actividad and every published doc. Leo, Adriana, Michelle, Jesús and the field techs work from it. The vault keeps the distilled memory; Drive the client exports; the site is where work is coordinated and closed. Mechanics (what lives where, how to edit each piece): hbox-docs/CLAUDE.md.

Start of every task — read the state: hbox-docs/_estado/tablero.md (board snapshot; if missing or older than a day, ask Leo for ./scripts/tablero.sh foto), hbox-docs/docs/datos/proyecto.json (Ruta, hitos), §0 below, hbox-docs/docs/hardware/index.md.

End of every task — the closing loop. A task is not done until each item that applies is on the site:

Board. Write a lote hbox-docs/backend/lotes/AAAA-MM-DD_tema.json: close what's done, open what's next (owner + date), comment on what moved, every change with a one-line why in es-MX. Reuse ids from the snapshot; buscar by title when unknown; si_no_hay before creating. Format: hbox-docs/backend/lotes/README.md. Claude never writes the board directly; Leo runs ./scripts/tablero.sh revisar → aplicar.
Docs. Source in the NN- folder (AAAA-MM-DD_Drogheda_…, date: front matter, es-MX for the team) → hbox-docs/scripts/sync-docs.sh MAP → mkdocs.yml nav (Auditorías y pasadas; superseded → Historia, with a banner) → section index (docs/hardware/index.md …) → Bitácora entry. Figures on the site with the doc they explain. Copy to the claude.ai Project (claude/…).
Ruta. hbox-docs/docs/datos/proyecto.json when a board changes stage, a date moves or the week's focus changes (enfoque_inicial). The live «Enfoque de la semana» is Leo's and Adriana's: propose the wording.
Decisions. hbox-docs/docs/tableros/ingenieria.md «Últimas decisiones» (dated, newest first, with the D-xx-n number) and §0 here.
Improvements. If the site got in the way (stale data, missing view, broken link, wrong doc), fix it in the same task when small; otherwise a pendiente in the lote (etiqueta «sitio») and a line in the site plan (claude/2026-10-20_Drogheda_Sitio_Inicio-y-Tablero_Propuesta.md, Phase 2b/3).
Master index. §0 status paragraph + §2 directory row (this file). Vault notes only when something becomes evergreen (decision, lesson, milestone): Second Brain/03 Projects/Helgen/Project-Drogheda/.
Hand-off. End the reply with a «Centro de mando» block: what changed on the site, the lote (if any), and Leo's commands — sync → mkdocs build --strict → commit/push hbox-docs → bump the submodule → deploy.sh → tablero.sh revisar / aplicar → restart actas-hbox only if backend/app.py changed.

0. Where we are (2026-06-20)

Helgen deployed HBOX RTK trackers on heavy port equipment at Hutchison Ports ICAVE (Veracruz). They worked "ish," then failed. We are mid-crisis and hardening the product for scale. Three independent failure fronts, all being fixed in parallel:

Backend (confirmed in code). The production retranslator.py blocks the whole fleet on any upstream slowness, and an anti-jump filter can permanently black-hole a healthy unit → some "dead" units may be backend victims, not dead radios. See 02-Architecture-Software/backend-review.
Thermal (component-level). The ASA HBOX (UV-stable, softens ~95–100 °C — the case is fine) sits sealed inside a sealed ABS IP67 cabinet that also holds the Mean Well supply → nested heat trap that cooks the battery / boost / modem in full sun. See 06-Testing-Validation/RCA-2026-06-field-failures.
Prototype hardware. Dupont, hand-wiring, 18650 + PowerBoost — the client's (ICAVE) own indictment. Fix = ruggedize now + production PCB.

Status of units: all pulled from machines. 4 in hand (3 dead, 1 working-ish), physically in Veracruz; team in Querétaro → remote debug. Units run firmware v1 (no thermal log). Triage: 06-Testing-Validation/remote-diagnostic-protocol.

Commercial reality: productized across ICAVE, TIMSA, EIT, LCT (Hutchison terminals); target 30 units operational by August; hundreds of cabinets planned. The fix must be production-grade and repeatable.

Logs & observability (2026-06-20). Analyzed the first real bench + healthy-baseline log set (u-blox .ubx, 4G-NTRIP console .log, server retranslator tcpdump) + the caster/F9P config. GNSS receivers are healthy but no unit reached RTK — all SPS (corrections not applied: free rtk2go caster + RAM-only F9P config + indoor sky). The 4G-NTRIP console is an unreliable health signal (see §6 — "master-14 fault" retracted; only master 21 confirmed). Built hbox-log-tools (Log Explorer + analyzer + dashboard + manual) and a Blackpill v2.1 logging spec to fix observability. Canonical: 06-Testing-Validation/2026-06-20_Drogheda_GNSS-Findings-Summary.md.

Electrical / PCB (2026-06-24). Watchdog v3 KiCad schematic (03-Architecture-Hardware/kicad/hbox-watchdog-v3.kicad_sch, ERC-clean). DFR1015 folded on-board → GX16 pin 3 now carries RAW machine ignition (12–24 V), not pre-conditioned 5 V. Battery re-added with a proper charger — LTC4040 + NTC temperature-qualified charging on the 1S4P pack; the Blackpill cuts charge when the cell is hot (answers the RCA's #1 failure). Added reset (on-board + external), a 4-LED battery gauge, and a power-cutoff switch; fixed two real schematic bugs (EXT_LED disconnect, panel-LED short). Proto = 3 boards of easy-to-find parts (watchdog-protoboard-BOM-3boards.xlsx + Spanish shop list watchdog-LISTA-DE-COMPRAS-ES.xlsx). Canonical electrical state → 03-Architecture-Hardware/watchdog-electrical-design-state.md — read first for any electrical context.

PROD schematic complete + PCB layout kickoff (2026-07-02). hbox-watchdog-v3-PROD.kicad_sch now carries all blocks — ERC 0 errors: LTC4040 Block B sized to the 12 Ah pack (RPROG 825 Ω → 2.42 A ≈ C/5 · RS 8 mΩ → 3.1 A input limit · PFI trip 4.60 V · backup 4.79 V · charge 4.00 V Li-ion via VSYS-referenced straps), Block E cutoff (P11, MAIN5V→SYS5V), Block F PA4→VEH5V re-tap, Block H fail-safe Modo-B bypass (K1 normally-closed signal relay — corrections survive a dead/absent MCU), Block I NTC→PB1 (block 11). New MCU pins live: PB1 · PB3 · PB4 · PB5 · PA8. Same day (PM): CARRIER-BOARD conversion — the PROD board now sockets all three modules on female headers: Blackpill (J1/J2) + simpleRTK2B Pro as UNO-form shield (MOD1, D0/D1=UART1, D2=RX2, D8=TX2, IOREF=3V3, 5V=SW_5V) + 4G NTRIP Master on an on-board XBee socket (J7/J8 2 mm; VCC = 3V3_MODEM, a second MP1584 buck off SW_5V — the HP XBee socket is 3.3 V not 5 V). Modo B + K1 NC bypass = permanent uplink; RTCM3 downlink direct; P3/P13/H3 DNP. Board 120×100 mm, shield field with SMD-only underneath, XBee field right, access parts outside; ERC 0; carrier DRC baseline saved (…-drc-carrier-baseline.txt; ~29 sub-mm placement kisses + by-design under-shield courtyard overlaps). Next gate: placement review vs HBOX/cabinet mechanicals (+ verify D2/D8=RX2/TX2 on a physical Pro), then routing (5 V ≥0.5 mm, SW_5V ≥0.8 mm per kicad-guide). Fab gate unchanged: bench-validate the LTC4040 backup + hot-cell charge cutoff on the proto first. Latest proto assumptions ledger = Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx (Estado y cambios) + Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf (LaTeX source in repo: Guia-Conexion-Protoboard/). Wiring diagrams v2.1 (blocks 1–11) in circuitikz-wiring/; client decks Avance + RCA refreshed to v1.1.

Proto sensor suite realigned to parts in hand (2026-07-03). No SHT40 (long lead) → proto Block 6 = AHT10 (0x38 fija, 3V3 only, alone on I²C1 — Aosong restriction); LM35 → PA7 (last free ADC channel) joins NTC→PB1 → triple temperature (3 technologies, 3 electrical paths); humidity = AHT10 only. SHT40/TMP102 stay PCB-only (PROD schematic untouched). The kit's TP4056 exposes no TEMP pin → charger-NTC unused on proto; new PA8 CHRG_RUN high-side cut of TP4056 IN+ (2N3904+IRF9540N; HIGH = charge, MCU absent = no charge — inverted vs PROD CHRG_EN, firmware flag). Cutoff switch now wired: nodo SYS (OR merge) → SPST → MAIN5V (= Block E/P11, kills vehicle AND battery). Caps in hand 100 nF/10 µF/100 µF; fan confirmed 2-wire. Docs synced: ledger xlsx · Guía v2.2 · circuitikz v2.1 · both proto BOMs · design-state (canonical).

EinarBoard 1.0 Rev 1.1 — audit closed, order-prep pack (2026-07-07). The PROD carrier is officially Helgen EinarBoard 1.0 (title-block EINARBoard HBOX 1.0), 135.1×100.1 mm (grew from 120×100 on Jul-3). Pre-fab audit (03-Architecture-Hardware/2026-07-06_…PreFab-Audit_v1.0.md) CLOSED: H1 Q7 S/D corrected (S=VIN_SW, D=MAIN5V) · H2 Q5/Q6 → Q_NPN_BEC · H3 Rig 22k (+ DFR1015 removed — raw 12–24 V → 22k/10k divider + BAT54 clamp → PA5) · H4 SW_IN → PWR_MID 1.0 mm; ERC 0 / DRC 0; M3 closed on a physical Pro (switchless variants: XBee socket hardwired to UART2 — never plug the Pro's USB-XBee port in service) · M4 HBOX fit verified → bare-board order RELEASED; fleet PCBA still gated by M2 (LTC4040 bench validation) + LCSC re-confirm at upload. Order-prep pack in 03-Architecture-Hardware/EinarBoard-Manual/: einarboard-manual.tex → branded 21-pp PDF (embeds the Rev 1.1 schematic full sheet + F/In1/In2/B layer plots + silk assembly view, exported fresh from the Jul-7 saves into assets/; the Jul-6 …-PROD-schematic.pdf/-blueprints.pdf at 03-AH root are stale — pre-H1/H2) · helgen_einarboard_1.0_production_bom.xlsx (Summary + Internal PCBA w/ verified LCSC + External Integration, live formulas) · tools/generate_production_bom.py + tools/sync_bom.py (Excel→pcba_bom.tex + external_bom.tex — both BOMs in the report; the workbook is the BOM source of truth) · scripts/prep_order_release.sh (safe cleanup + release commit; dry-run default). KiCad sch↔board sync is manual (F8 retired). Vault note: EinarBoard 1.0 — System Overview & Toolchain.

Guía de protoboard v3.0 + 4G alternatives (2026-07-08). Guía rewritten for a low-experience technician: new visual parts catalog (Guia-Conexion-Protoboard/ modulos-pinout.tex) — physical top-views of every IC module (LM2596 · MT3608 · TP4056 · AHT10 · DFR1015), full Blackpill 40-pin physical map (used pins colored, VB/B12 corner check), simpleRTK2B Pro with its real silk names (RX1/TX1/RX2/TX2/IOREF + XBee switch), 4G NTRIP Master + BOB-08276 breakout, TO-92/TO-220 pinouts, diode/LED/cap polarity, resistor color codes, protoboard anatomy + pre-power checklist; per-block «Piezas de este bloque» lines. Bloque 9 reworked around the XBee pitch: the 4G is 2.0 mm (not 1.27 — 10 pins = 18 mm) vs protoboard 2.54 mm → bridge options (★ BOB-08276 + 2× PRT-08272 ≈MX$100, SANDOROBOTICS CDMX, 1–2 days) + soldering steps + modem VCC = 3.3 V from SAL via dedicated buck (mirrors 3V3_MODEM; never 5 V) + bulk cap for LTE bursts. Also fixed: IOREF→3V3 rows added to Blocks 8/9 (missing in v2.2 — Pro UARTs are dead without it), Blackpill USB + 5 V rail never simultaneous warning, and the circuitikz socket label corrected 5 V→3.3 V (wiring-blocks.tex; lámina + Beamer PDFs rebuilt, still content-v2.1). Cheap-4G survey → 2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md: bench = keep Ardusimple on breakout; experiment = LILYGO T-A7670SA (~US$33, TinyGSM NTRIP, ~1 day fw); Aug 30-unit run stays Ardusimple (€112 @ ≥50); scale = A7670SA raw (US$9.4, NTRIP-over-AT fw) or Digi XBee 3 LTE Cat 1 (US$76, socket drop-in, MicroPython NTRIP on-module). Avoid -E band variants, SIM7000G (Telcel LTE-M provisioning risk).

Production audit V5.6 / V5.7 / v6 (2026-10-16). None is ready to order. V5.6 (hbox-watchdog-v5, kicad 5a93232) is close: pass 3 of layout (~1 day) + firmware 0.7.0 (board_v56.h, also runs V5.7 — same MCU pins) + a 5-board pilot. V5.7 (hbox-watchdog-v57, a7c0116): V5.6's pass-2 power fixes were not replicated (/BAT_PLUS on In1 at 0.5 mm again), U25 EP has 0 vias, FB divider 22 mm away; input range without the SD-15B = 9–32 V DC (TVS D10 SMBJ33A is the ceiling; recommend SMBJ33CA). v6: PCB never updated from the verified schematic (70 parity diffs incl. JP2 Li-ion, R52 open) and no firmware replaces the 4G NTRIP Master yet. Findings that apply beyond one board: the 7 V5.5 production holes (MH5/MH6/MH4 3.2 mm, MH4 at (185.2, 90.3) — 193.2 is only the old footprint anchor; MH7/MH9/MH10 ArduSimple; MH11 clamp) were lost from V5.6/V5.7 by Update PCB → restore with kicad/tools/t25_mounting_holes_v55.py (board-only footprints); and the LTC4040 input limit is ≈ 1 A instead of 2.5 A on V5.5/V5.6/V5.7 (VIN/CLN sense taps include ~19 mm of copper; fix = Kelvin to RS1 pads). D8 (identify v6 by the SC7A20) no longer works — V5.6/V5.7 have it too. Canonical: 03-Architecture-Hardware/2026-10-16_Drogheda_Auditoria-Produccion_V5.6-V5.7-v6_ES_v1.0.md

Michelle's 2026-10-16_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-3_ES.md (site: hardware/auditoria-produccion-16oct/).

v6 production audit + weekend plan (2026-10-16 PM) → re-audit of all three + T30 (2026-10-19). Audited on HBox_PCB 4f4681f (Michelle's pass 3 + Leo's merge fix). V5.6 (hbox-watchdog-v5, 240e2c3) is almost ready: /BAT_PLUS off the inner layers, /3V3_MODEM 1.0 mm, U7 EP 4 vias, no loose copper, RS1 Kelvin intact; DRC = only the 3 MOD1 NPTH-in-courtyard errors (by design), 0 unconnected. T30 (kicad/tools/t30_v56_v57_mecanicos.py; dry-run by default, .T30bak, aborts on geometry drift, DRC-verified on copies) adds parallel vias at every single-via power layer change, turns the 4 "micro" vias into through vias (/NTC 0.3/0.1 → 0.5/0.3), takes JP/TP/MOD1 out of BOM/CPL (PCB + schematic), sets title block + JLC04161H-7628 stackup; on V5.7 also +11 GND vias at U25 and deletes 12 loose items. After T30, V5.6 needs ~1 h of layout (L7 ≤ 5 mm from U7 + Dbk2, U6 VSYS 0.3 mm escape, 3 single vias, DRC exclusions) → Gerber/BOM/CPL → 5-board pilot. V5.7 (f3f35f4) now replicates V5.6, but /SYS5V runs 10.9 mm on In2 at 0.5 mm under K1 (blocker) and the U25 input loop is 52 mm² (target < 30) → ~half a day. v6 (00a9af4, only +15 GND vias since the audit): NOT READY, the 8 blockers of the 16-oct v6 audit stand (U25 still the AP64350 part code, no mounting holes, 5 V on In1/In2 at 0.5 mm, charger U6, U25 layout, modem RF on In1, GND vias, stackup); T25 --set v6 + T28 (kicad/tools/t28_v6_mecanicos.py) still apply; weekend plan rev 1.1 shifted one week (24–25 Oct, 31 Oct–1 Nov, pilot of 20 ordered Mon 2-Nov, G2 ≈ 22-Nov; JLC pre-orders not shifted). Merge incident (19-oct): 40decf8 wrote git conflict markers into both V5.x PCBs — Michelle's branch from f65c830 vs the Friday 18:00 auto-sync (2889ba2) of KiCad files from Leo's Mac; fixed in 240e2c3 + .gitattributes merge=binary (4f4681f). Rule: one person per board at a time, scripts only with KiCad closed and a clean tree; recommended: keep kicad/ out of the auto-sync (decision D-19-3). Canonical: 03-Architecture-Hardware/2026-10-19_Drogheda_Re-Auditoria_V5.6-V5.7-v6_ES_v1.0.md + 2026-10-19_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-4_ES.md (Michelle) + 2026-10-16_Drogheda_Auditoria-Produccion_v6_ES_v1.0.md + 2026-10-16_Drogheda_Plan-Fines-de-Semana_v6-Produccion_ES.md (site: hardware/re-auditoria-19oct/). V5.6 triage (2026-10-19 PM, on Leo's 18:59 working copy after T30 7650b96). One critical item, new and inherited from V5.5: U6 (LTC4040) has no capacitor at its VSYS pins 1/24 (nearest C34 10 µF at 11.5 mm, C32/C33 47 µF at 15 mm, all behind vias). The datasheet ranks the VSYS cap above everything else (single hot loop: buck 2.25 MHz / boost 1.125 MHz; VSYS abs max 6 V). Fix = add C129 10 µF 0603 X5R 10 V (LCSC C19702, basic) vertical at ≈ (153.07, 111.95) with a GND via, rerouting /PROG, /CLPROG_TP, /CHRG_EN (U6 pins 2–4); no part moves. The 18:59 save also lost T30's two /MAIN5V vias at (145.15/146.15, 97.6) and put /3V3_MODEM through 2 single vias. L7 (8.8 mm from U7) and the V5.5-inherited converter layouts (L6 11.7 mm, L8 35 mm from U12, Dbk1 18 mm from U2) stay for the pilot and are measured on the bench. Canonical: 03-Architecture-Hardware/2026-10-19_Drogheda_V5.6_Clasificacion-Criticos_ES_v1.0.md (site: hardware/v56-clasificacion-19oct/). T31 — C129 in, Dbk2 out (2026-10-20). kicad/tools/t31_c129_vsys_quitar_dbk2.py (dry-run by default, .T31bak, deterministic UUIDs, aborts on drift, idempotent) applied to both V5.6 and V5.7 schematics: C129 10 µF 0603 X5R 10 V (CL10A106KP8NNNC, C19702) on /MAIN5V–GND next to U6 (the missing VSYS cap); Dbk2 removed (U7 AP64350 is synchronous → D-19-2 resolved; the deleted diagonal wire was U7.8's only link to SW3_NODE, so U7.8 now carries its own SW3_NODE label); V5.6 also loses a stray no-connect flag on U10.14 (SC16IS752 SDA, wired to I2C_SDA — KiCad's ERC reports it only depending on read order). Verified on copies: ERC identical (0 errors), netlist only +C129/−Dbk2, schematic parity = exactly "C129 missing" + "Dbk2 extra". Next: Leo runs F8 on both boards (C129 arrives unplaced); Michelle places it at ≈ (153.07, 111.95) — same spot and same 3 signals to reroute on V5.7 — and deletes the Dbk2 branch (V5.6: 5 F.Cu tracks, 18.6 mm; V5.7: 4 tracks, 18.3 mm). Pasada-4 instructions → v1.1 (§0b, A-1, B-0, B-3); figure img/2026-10-20_Drogheda_T31-C129-y-Dbk2_v1.0.png. Audit of Michelle's pass 4 (2026-10-21; HBox_PCB 85e7602 V5.6, 1416dcb V5.7; T31 + F8 in, parity = only PF).* Both boards: C129 placed at (152.2, 111.8) and tied to U6.1/24 on F.Cu; Dbk2 branch gone; U7 rotated 180° (not in the plan) → L7.1–U7.8 4.0 mm (V5.6) / 0.4 mm (V5.7), SW node 13 → 10 / 6 mm, but U7.2 (VIN) now 5–6.5 mm from C119–C121, fed through ONE via under the IC, COMP node 13 → 23 mm. V5.6 NOT READY: new short /MODEM_EN–GND at R106.2 (R105/R106 moved 1.75 mm, the MODEM_EN track end now sits on R106's GND pad → modem never powers) + /SYS5V B.Cu at 0.09 mm from a U7 EP via (DRC errors). Both: VSYS→/MAIN5V down to ONE via, C129 GND has no via (0.25 mm track only), RS1 entry via moved onto the RS1.1 pad edge and its 2nd via dangling; V5.6 3V3_MODEM still 2 single vias. V5.7: K1 blocker solved (/SYS5V off In2), L22.1 2.3 mm from D34.1, but C149/C150 untouched (U25 input loop 52 mm²) and single vias on the 5 V path ((168.0, 110.6) + (162.85, 113.19) carry all of U25 → RS1; (145.9, 57.6) is only the C78/C30 bulk + NTC/5V_SENSE divider branch — corrected PM, the AM text said all of U25's output); 4 one-layer vias. Lesson: DRC with --refill-zones needs the project .kicad_dru in the copy, else false unconnected items. Decision D-21-1 for Leo: C130 100 nF 0402 (C1525) at U7.2. Canonical: 03-Architecture-Hardware/2026-10-21_Drogheda_Auditoria-Pasada-4_V5.6-V5.7_ES_v1.0.md (site: hardware/v56-v57-auditoria-21oct/). T32 + T33 (2026-10-21 PM; D-21-1 approved by Leo). kicad/tools/t32_c130_vin_u7.py (both schematics; imports T31's helpers, so both stay in tools/): C130 100 nF 0402 X7R 16 V (CL05B104KO5NNNC, C1525) /SYS5V–GND = U7.2 VIN bypass; ERC identical, netlist only +C130. kicad/tools/t33_v56_v57_auditoria_21oct.py (both PCBs; per-board plan embedded as JSON; dry-run default, .T33bak, uuid5, aborts on drift): V5.6 R106 short removed (MODEM_EN track now ends on R105.1) and /SYS5V under U7 narrowed 1.0 → 0.7 mm (0.24 mm to the EP via); both: 2nd VSYS→/MAIN5V via; V5.6 +2 vias at each /3V3_MODEM layer change and at /SYS5V (136.97, 86.96)/(146.37, 86.96) (U12 = MP1584 /3V3_ETH branch); V5.7 +2 at /SYS5V (158.6, 57.925) and (136.97, 86.96), via (163.79, 113.19) joined on B.Cu so (162.85, 113.19) is backed; 5 one-layer vias + a 0.14 mm stub deleted. Verified on Mac copies (DRC with .kicad_dru + refill + parity): only the 3 MOD1 errors, 0 unconnected, 0 dangling; parity = "C130 missing" + PF*. Left for Michelle (pass 5, audit section 3): F8; C130 at U7.2 with its own GND via + 2nd U7.2 feed via (needs EN/FREQ/COMP moved ~0.8 mm); C129 GND via(s) (move PROG/CLPROG_TP/CHRG_EN ~0.5 mm); 2nd RS1 entry via; V5.7 C149/C150 + (168.0, 110.6) (+ (145.9, 57.6) if it fits); MH7/9/10 exclusions; optional Rcomp2/Ccomp2/Rfreq2 closer (COMP 13 → 23 mm after the U7 rotation). The planner found no room for those, nor for V5.7 (146.37, 86.96) (U12 branch, accepted 19-oct). Lessons: deleting a via can leave a sub-mm stub (delete it too); a new via with a long stub can split a GND pour island (1 unconnected) → always re-run DRC with parity on the copy before applying. Figure img/2026-10-21_Drogheda_T33-Arreglos-y-Pendientes_v1.0.png. 21-oct night: v6 T25 + T28 applied; V5.6/V5.7 pass 5 reviewed. T28 (and T25 --set v6) had never been run (the plan had them for Sat 24, 8:00). Applied by Claude on Michelle's 9255b84 after a copy test (KiCad 10.0.4 DRC with .kicad_dru, refill, parity): 22 new errors, all at MH4 (D23/D24 inside, /NTC In2, /SIM_RST, a GND track) and MH8: Michelle had moved D34 + 2 GND vias into the v6 corner hole, invisible because the holes were missing; 0 unconnected; parity = 19 PWR_FLAG. T28 closes v6 blockers 1 (U25 LCSC Part) and 8 (stackup) + U6 paste 50 %, 114 solid pads, RF 0.35, title block. v6 block A progress: L22.1 2.2 mm from U25.8, 6 EP vias, C149 0.75 mm, 5 GND vias at D34.A, /VEH5V L22 → RS1 all F.Cu 1.0 mm, 0 vias — but D34 is now 13 mm from the SW pin (hot loop ≈ 47 → ≈ 115 mm²) and R53/R54 (LTC4040 BSTFB, belong ≤ 3 mm from U6.18) sit in D34's spot. Blockers 3 (/VIN_SW In2), 4 (U6), 6 (RF LTE In1), 7 (111 GND vias) unchanged. V5.6/V5.7 pass 5 (6458c5d): DRC only MOD1, parity only PF*; C130 placed 1.8 mm from U7.2 with its own GND via (both); V5.6 C129 GND via; V5.7 (168.0, 110.6) doubled. Regression in both: the moved RS1 entry via now sits ON the 0.25 mm U6.6 VIN sense trace → not Kelvin (≈ +0.3–0.4 mΩ, input limit −3–4 %); the new "2nd RS1 via" (149.48, 118.8) is F.Cu-only (dangling). Still open: U7.2 single input via, V5.7 C149/C150 not rotated (loop ≈ 56 mm²) and no C129 GND via, MH7/9/10 exclusions, stubs (/RS485_B V5.6, /24V V5.7). Lesson: "move the via off the pad" must also say "not onto the sense trace"; re-run kelvin2 after every change near RS1. Canonical: 03-Architecture-Hardware/2026-10-21_Drogheda_Estado-v6-T25-T28_ES_v1.0.md (site hardware/v6-estado-21oct/) + §5 (pass 6 list) of the 21-oct audit. 21-oct night, later: pass 6 done by Claude with T34–T37 (Michelle out; Leo: "start step by step, V5.6 first"). kicad/tools/t34_v56_pasada6.py (V5.6: RS1 Kelvin restored — U6.6 sense rerouted (151.55, 115.8) → (151.55, 117.7) → pad 1 from its inner side; 2 /VEH5V entry vias 0.6/0.3 at (150.7, 115.9)/(150.9, 116.6) joined on F.Cu + B.Cu; dangling via (149.48, 118.8) and the 0.01 mm /RS485_B stub deleted; MH7/9/10 DRC exclusions written to .kicad_pro) · t35_v56_via_u7.py (V5.6: 2nd U7.2 input via (138.7, 117.45)) · t36_v57_pasada6.py (V5.7: same RS1 fix, U7 via (138.925, 116.525), /24V B.Cu dead end trimmed to (182.4, 69.4), exclusions) · t37_v57_c129_gnd.py (V5.7: C129 GND via (151.25, 112.5), 0.18 mm from the pad — room made by moving the /IGATE and /F0_SEL B.Cu horizontals and a 0.74 mm 45° bump of /CHRG_FAULT + /CHRG_STAT on In2). All: dry-run default, uuid5, .T3xbak, abort on drift, idempotent; tested on Mac copies (KiCad 10.0.4 DRC with .kicad_dru + refill + parity), then applied to HBox_PCB (same SHA-256 as the copies). Both boards now: only the 3 MOD1 errors (excluded), 0 unconnected, 0 dangling, parity only PF*, RS1 Kelvin on VIN and CLN, every mounted part with LCSC → copper ready for Gerber (next: Leo commit/push, B + DRC in KiCad, Fabrication Toolkit Gerber/BOM/CPL). V5.7 C149/C150 rotation dropped — proposal D-21-2, needs Leo's OK: of the ≈ 56 mm² pad-centre loop, ≈ 40 mm² is U25 → D34 alone (VIN and SW on opposite sides of the HSOP-8, D34 above it) → ≈ 46 at best by rotating, < 30 needs D34 moved; and In1 is solid GND under the whole stage (207/208 mm², 0.21 mm below F.Cu), so the HF return mirrors the forward path → bench-check SW/VIN ringing at 9/24/32 V, 2.5 A. Lesson: over a solid plane the pad-centre polygon overstates the hot loop; judge forward-path length (SW pin → diode) and GND vias at Cin− and the anode. Optional left: V5.7 /VEH5V (145.9, 57.6) 2nd via (C78 branch), U7 compensation closer. Canonical: §6 of the 21-oct audit; figure img/2026-10-21_Drogheda_Pasada-6-T34-T37_v1.0.png. 21-oct night, later still: T38 on the real v6 (Leo: "work on the real V6"). kicad/tools/t38_v6_courtyards_mh.py (no part moved): (1) the 8 easyeda2kicad footprints of Drogheda-v6.pretty had courtyard = body outline with every pad outside (L22's was a triangle) → the DRC was blind on U19/U20/U23/U24/U25/U26/D22/D27/J12/J13/L22. New courtyard = bbox(body ∪ pads) + 0.25 mm, written on the board AND in the library (v6 lib-mismatch count unchanged, 81). It exposed 14 overlaps: 13 margin-only (physical gap 0.29–0.76 mm) and 1 real (C153, 1210, 0.3 mm under L22's body). Exclusions can't be scripted: KiCad matches type|x_nm|y_nm|uuid|uuid on the exact marker position, which only its own DRC computes (tested: footprint-anchor positions don't match) → Michelle excludes them in the GUI at the end. V5.6/V5.7 use 2/4 of these footprints (U7, U26; + U25, L22 on V5.7) and were not touched: their DRC now shows 2/4 "doesn't match library" warnings (courtyard only; with the new courtyard they'd have only margin overlaps, 0.40–0.56 mm) → don't update those footprints before their Gerbers. (2) New finding: the v6 B.Cu is a /3V3 plane and reached 1.85 mm from all 5 MH centres, inside their 6-mm mask openings (both faces): bare 3V3 under the standoff/insert, bare GND under the screw head → 3V3–GND short through metal hardware. Rule added to hbox-watchdog-v6.kicad_dru (outer layers, A.Type == 'Pad' && A.memberOfFootprint('MH*') && B.NetName != 'GND' → hole_clearance 2.4 mm = 4.0 mm from the centre); the zone filler honours it (B.Cu /3V3 now exactly 4.0 mm at all 5; F.Cu GND stays at 1.85, as V5.5) and the DRC now flags MH4's /SIM_* (11 errors). V5.6/V5.7 don't have the problem (outer pours GND, /3V3 on In2). (3) MH6: /3V3 3.02 mm on F.Cu → via (61.6, 130.3)

B.Cu along y = 130.3 / x = 69.5 to H4.1, 4.06 mm. DRC 22 → 52 errors, all known (MH4 28, MH8 10, courtyards 14); 0 unconnected; parity 19 PF; warnings unchanged (262). Block A correction: rev 1.0 of the v6 state said "L22 stays, D34 goes below pin 8" — impossible (U25-to-P1 gap 4.1 mm < D34's 6.7 mm) → proposal α for Michelle (D-21-3, needs Leo's OK): R53/R54 next to U6.18 first; D34 rot 90 at (181.0, 121.75) (cathode 3.4 mm from the SW pin); L22 at (192.1, 122.5) (L22.1 8.7 mm; 0.62 mm copper-to-edge — check the HBOX wall); 4 GND vias at the anode; /VEH5V out of L22.2 under the inductor body (y 116–118) to R51.1; In1/In2 cleared under SW/L22; MH8's 2 GND vias deleted. Plan targets corrected (plan rev 1.3): D34.K ≤ 3.5 mm, L22.1 ≤ 9 mm, SW copper ≤ 10 mm² outside the pads (the pads alone are 33 mm²), pad-centre loop ≤ 60 mm² (today 115). MH4 stays with Michelle (SIM ESD re-placement + reroute). Canonical: v6 state doc rev 1.1 (§3, §5); figure img/2026-10-21_Drogheda_v6-T38-Courtyards-U25-Barrenos_v1.0.png. Lessons: easyeda2kicad footprints ship body-only courtyards — sweep "pads outside courtyard" on every imported footprint; and check pours, not only tracks, against hardware keep-outs. Final production audit of V5.6 + V5.7 (2026-10-22; Leo: "all my other sessions say we're almost production ready… boards are to be ordered today"). Protocol first (03-Architecture-Hardware/2026-10-22_…_Protocolo_ES_v1.0.md, the "reprompt"), then the audit on the fab packages production/HBOX_v5_Rev6_PROD (V5.6, hbox-watchdog-v5) and HBOX_v5_Rev7_PROD (V5.7, hbox-watchdog-v57). Verdict: GO for the 5 + 5 pilot today with three order conditions that touch no copper — (1) JLC Epoxy Filled & Capped vias + X-ray on U6 (3 thermal vias inside the 50 % paste windows of the 0.5 mm QFN: the V5.5/V4 bridging cause); (2) rotation/polarity check in the JLC viewer for U6, U7, U25, U26, L22, Q7, U16, D34, D10 and the electrolytics (easyeda2kicad footprints never fabbed, no Toolkit rotation table); (3) BOM D10 SMBJ33A → SMBJ33CA (C8838 / C2688178; the unidirectional part opens SMD fuse F2 on a reversed harness). NO-GO for the 108 / 322 until the pilot passes the bench with firmware 0.7.0 — no firmware enables the modem of these boards today (MODEM_EN = PC3 is new; 0.6.3 also reads the NTC on the wrong pin, floats at 4.00 V instead of 3.50 V LFP and reads ignition digitally — 12 V lands at 1.38 V, undefined). Package verified: Gerbers identical to a kicad-cli regeneration with a fresh, project-aware zone fill (0.000 mm² XOR; masks/paste/silk/drills identical), DRC = only the 3 MOD1 errors, 0 unconnected, parity only PWR_FLAG, RS1 Kelvin on VIN and CLN on both, BOM/CPL = PCB (226/229 placed, all with LCSC). P-1: both repo .kicad_pcb carry the pass-5 zone fill (the Toolkit refilled at export; a non-refilled export shorts GND onto the T35/T37 vias) → Leo opens, B, saves, commits; rule D-22-3: every T script that touches copper ends with a GUI refill before the commit (lesson: headless refill without the .kicad_pro beside the board gives a different fill — copy the project, not just the board). Electrical: LTC4040 (PFI 4.40/4.51 V, backup 4.79 V, 2.5 A Kelvin, 1.40 A, 3.50 V LFP, NTC +10…+60 °C), AP64350 modem rail (3.33 V / 500 kHz from SYS5V, EN off by default, C130, C43 220 µF — the V5.5 modem brownout is gone by design), TPS54360B (5.32 V / 600 kHz, 9–32 V, EN floating) all checked against the datasheets. Ports usable with two rules: RS-485 DE//RE hang on RTSA (transmitter on from reset until the firmware writes EFCR — ~1 s bus hold) and H4 (TTL) vs P16 (RS-232) never together (shared SER_RXB); for 108/322 swap SP3485 → THVD1410DR (C2671345) and MAX3232 → TRS3232E (P-5, same pinout). Battery: 2.9 W avg / 8.7 W peak (< 12 W boost); sleep floor ≈ 75 mW only with the W5500 in PHY power-down (no 3V3_ETH enable, E-3) → ≈ 5 days at 45 s every 10 min; thresholds LFP 2.95 / 3.20 V; 10-min cycle = STOP + RTC (LSE FC-135 with 12 pF caps runs fast, LSI fallback) + SC7A20 INT1 (PB9) + ordered power-down (MODEM_EN, PA1, K1 released, UARTs Hi-Z). V5.7-only: ignition 12 V → ADC with 0.80/0.55 V hysteresis (E-7); U25 input loop ≈ 56 mm² stays (D-21-2 holds) and is bench-checked at 9/24/32 V, 2.8 A; two series input vias (E-10). 30 findings (P-1..P-8, E-1..E-16, F-1..F-8), 16 risks (5×5 before/after), 6 easy wins. Deliverables: 03-Architecture-Hardware/ 2026-10-22_Drogheda_Auditoria-Final-Produccion_V5.6-V5.7_ES_v1.0.md (canonical, site hardware/auditoria-final-22oct/) · Auditoria-Final-V56-V57/ (LaTeX sources, 33-pp PDF, 19-frame Beamer, figures, scripts: gerb.py Gerber parser/renderer, gcmp.py primitive/XOR comparison, netparse.py, copper.py connectivity + Kelvin + cut-via test, riesgos.py) · 8 figures in img/ · 04-Source-Code/firmware/hbox_v5_bringup/board_v56.h (64-pin map from the 22-oct netlist, V5.6 = V5.7; needs the #elif defined(HBOX_BOARD_V56) include in the .ino) · lote 2026-10-22_auditoria-final (closes t-v56-revision-gerber, re-aims t-v56-piloto at today's 5 + 5 order with the checklist, t-fw-070 in progress with F-1..F-8 sized, creates t-p1-relleno-commit, d-22-1-go-piloto, t-preorden-108-322-bom). 0.7.0 work list: F-1 0.7.0-pre 1 day · F-2 backup cycle 3–4 days · F-3 SC16IS752 1 day · F-4 field Ethernet 2 days · F-5..F-8 2 days. 13:30 re-verification on Leo's 13:00 saves (V5.6 338ee14b, V5.7 85baca51, packages regenerated): saved fill = fresh project-aware refill (0.000 mm² both), package = file, copper and all 11 layers + drills identical to the morning audit, BOM/CPL same SHA (D10 still SMBJ33A → condition 3 stays), DRC unchanged → P-1 closed, verdict unchanged, commit pending. Only non-fill diff in the files = silkscreen text render_cache (cosmetic). Re-check tooling kept in Auditoria-Final-V56-V57/scripts/: verify_mac.sh (kicad-cli DRC + as-saved Gerber + project-aware refill.py + Gerber) and gcmp_b.py (A saved-vs-fresh · B package-vs-file · C/D vs the audited copper) — 5 min after any change, before paying; the quick wins run in a parallel session.

22-oct: T39 — v6 block A done by script (Leo, 09:40: "do the changes on V6, it's the priority"). kicad/tools/t39_v6_bloque_a.py (requires T38; drift-checks every part/track it touches; idempotent; .T39bak). Proposal α applied: D34 rot 90 at (181.08, 121.75), L22 at (192.18, 122.5) — 0.08 mm east of the proposal so D34's courtyard doesn't hit C152's (U25|C152|D34|L22 is exactly full up to the 0.5 mm edge rule; L22.2 copper now 0.53 mm from the edge, body 1.26 mm → HBOX wall check still open); R53/R54 to (178.25, 109.6) / (178.25, 111.1) under JP2 (R53.1 on the JP2.1 /MAIN5V via, R53.2/R54.1 on the existing /VFB_BST via to U6.10/U6.18, R54.2 to a new GND via) — 3.4 mm from U6.10 but 6–7 mm from U6.18, so block B step 6 is only half done; SW node as F.Cu tracks (1.4 mm along y = 124.4 pin 8 → D34.K → L22.1, C152.2 0.9 mm); /VEH5V 2 mm from L22.2 up and under the inductor body to R51.1; 4 GND vias at D34's anode + 1 more at C149 and C150 + R54's; MH8's 2 GND vias deleted; In1/In2 cleared under the stage: /VFB_BST 24 mm and /MAIN5V 15 mm deleted, /I2C_SDA re-layered to B.Cu and /I2C_SCL rebuilt on B.Cu inside SDA (they crossed once on one layer), R121's 5 V sense to B.Cu. Results: D34.K 3.52 mm (target 3.5), L22.1 8.79, SW 9.8 mm² outside pads, pad-centre loop 56.5 (C149) / 60.8 (C150) vs 114.6 before; KiCad 10 DRC (refill + parity + --all-track-errors): 0 unconnected, parity 19 unchanged, errors 52 → 44 (≈ 33 MH4 + 11 pre-existing margin courtyards), warnings 262 → 254, one new warning (0.3 mm /MAIN5V tap, PWR_HI rule). Live file refilled with kicad-cli next to the .kicad_pro = byte-identical to the tested copy (97ea7e45) → meets D-22-3 (a project-aware CLI refill equals the GUI fill: V5.6/V5.7 CLI-refilled Gerbers are identical to the Toolkit's). Not committed yet. Lessons: (1) any F.Cu zone with priority above the GND pour makes KiCad 10 re-fill the whole F.Cu GND differently (40 k → 65 k points, +0.7 MB, 2 starved thermals far away at J11.B12/U26.1) — so the SW node/VEH5V are tracks, not zones; (2) KiCad 10 reports a different subset of MH4 pairs on every run of the same file (29–34 errors) → compare DRCs with --all-track-errors and treat MH4 counts as ± a few; (3) device_commit_files re-uses a cached upload for the same staged path → re-commit under a new name; (4) zip in the mounted folder fails (temp + rename) → use tar czf. Still open in block A: Rig1 4.79 mm from P1.3 (≤ 3), dead /24V (schematic decision), C150 2.31 mm from pin 2 (≤ 2; C149 0.75). Same day, independent check of the V5.6/V5.7 packages (agrees with the final audit): gerbv 400-dpi XOR of every layer vs a project-aware CLI regeneration = 0; after Leo's 13:00 refill + save the saved boards export identical Gerbers without refilling (P-1 closed for V5, not committed); extra notes: 19/18 THT parts are in the BOM/CPL (JLC will quote THT assembly), the Toolkit upper-cases designators in BOM and CPL (consistent, no collisions), and production/netlist.ipc is the V5.7 one (last run). Canonical: v6 state doc rev 1.2 §6 + plan rev 1.4; figure img/2026-10-22_Drogheda_v6-T39-Bloque-A_v1.0.png; lote 2026-10-22_t39-v6.

22-oct (afternoon): T40 — v6 MH4 freed by script. kicad/tools/t40_v6_mh4.py (requires T39; drift checks; idempotent; .T40bak; new SET_PT op shortens a kept segment along its own line, keeping its uuid; REF_MOVE moves only a reference). D23 (SIM_DATA TVS) rot −90 at (179.25, 87.0) under U19.31 (stub 1.95 mm, was 7.5); D24 (SIM_CLK TVS) rot −90 at (188.15, 87.6) between a new SIM_CLK via and R129/R133; D25 not moved. /SIM_CLK drops to In1 at U19.32 and runs at y = 86.7 to a via at (188.95, 86.7); /SIM_RST leaves D25.1 on F.Cu at y = 85.95 (4.225 mm from MH4's centre) to a new via (187.05, 85.95) on the same In1 diagonal (old via was 3.94 mm, rule 4.0); /NTC (In2) used to run through the MH4 hole (y = 89.7): the diagonal now turns at (179.8, 87.5), 0.95 mm from the hole edge. Found during the redesign: the F.Cu channel between U19's pad row and the new SIM_RST (0.8 mm) is too narrow for the pour (0.5 thermal gap + 0.3 clearance + 0.25 min width) → U19.92/U19.94 would be stranded → 0.25 mm GND track at y = 85.35 under U19.93 (BT_ANT, NC) + GND via (186.6, 84.6); GND via (183.0, 85.5) deleted. TVS GND vias: D23 0.83 mm, D24 1.06, D25 2.25 (track; was 1.25 via the pour). R129 (DNP) ref moved right so it doesn't sit on D24's silk. KiCad 10 DRC: 297 → 260, 0 new, 0 unconnected, parity 19; gone: 13 hole-clearance + 17 mask-bridge + 2 NPTH-in-courtyard errors + 5 silk warnings → v6 errors = the 11 margin courtyards only. Fills differ only inside a 29 × 24 mm window around MH4. Live refilled with kicad-cli = byte-identical to the tested copy (a273d44c). Not committed. Not done: L-38/B-09 "D23–D25 next to J14" — socket → TVS copper is 27–41 mm (DATA 28.6 · CLK 27.1 · RST 40.6) through the 22 Ω; the 28-sep decision to skip a /SIM_VDD array assumed L-38 → D-22-4 (Leo): (a) keep, or (b, recommended) move D23–D25 to /SIMB_* at J14's pins with a GND via each (schematic change + placement; T41 or Michelle). Canonical: v6 state doc rev 1.3 §7 + plan rev 1.5; figure img/2026-10-22_Drogheda_v6-T40-MH4_v1.0.png; lote 2026-10-22_t40-v6.

Command centre (2026-10-21, 20:00; Leo: «this is the command centre for all tasks»). Rule and closing loop in ★ above. Built the bridge that lets Claude's tasks reach the board: hbox-docs/backend/tablero.py (stdlib; foto / revisar / aplicar / pendientes through the live API as X-Remote-User: claude; ledger /srv/projects/drogheda/lotes-aplicados.json; never re-applies, never touches Hecho unless asked, refuses edited lotes) + hbox-docs/scripts/tablero.sh (Mac side; deploy.sh now refreshes _estado/ and reports pending lotes). First lote 2026-10-21_pasada-6: closes the pass 2–5 tasks and the V5.7 source/close tasks, puts t-v56-revision-gerber in progress for V5.6 + V5.7 (Leo + Claude, 22-oct), creates D-21-2 (Leo), the 5 + 5 pilot order (if not already there), the V5.7 bench task (Jesús + Claude) and v6 «D34 back next to U25.8, MH8 clear, R53/R54 ≤ 3 mm from U6.18» (Michelle, 24-oct); comments on the v6 tasks. Tested on a seeded copy of the real backend incl. a simulated 16-oct board. Site: Ruta/hitos/enfoque_inicial to pass 6 (V5.6 and V5.7 «Lista para Gerber», pilot ≈ 22-oct), Ingeniería decisions + Bitácora entries, «El sitio es el centro de mando» in the engineer's guide (v1.2), first rule on the home page. Vault: playbook + Drogheda memory set brought to 21-oct. Crisis mode (2026-10-22, 13:30; Leo). Project traffic light red. Causes: no payment received this month → operating tight, no significant purchases; TIMSA (Manzanillo) blocked by an administrative issue with our vehicle there; EIT (Ensenada) waiting for material shipped from Manzanillo; ICAVE (Veracruz) bad weather → short field windows, with faults that can only be investigated on site; software: a Wialon retranslator pointing to our server is missing (to compare RTK vs the legacy GPS in our monitor) and sudden disconnections must be investigated immediately. Immediate goal: 1–2 units installed per site. Paying suppliers unblocks most tasks. Board: lote 2026-10-22_crisis (cobranza, priority purchase list, purchases/pre-orders/ferretería blocked on payment, per-site install tasks, TIMSA vehicle, EIT material, ICAVE field investigation, Wialon retranslator, disconnections, field owner per site, periodic meetings). Site: tasks get sitios (icave · timsa · eit · lzc · qro; unset = Querétaro) with a site filter, new track Gestión, a home traffic light with per-site colors, and a Juntas page (standup + quick wins recorded with Gemini → Claude writes a lote → Leo applies). Deploy needs restart actas-hbox before tablero.sh aplicar. Installations per site (2026-10-22, 14:00; Leo: «a board per site for the installation… we don't know in which vehicles… we have installation goals and we don't have testing»). New Instalaciones board (/tableros/instalaciones/; hbox-docs/backend/instalaciones.py, GET /api/instalaciones, registered from app.py): every unit per site with its vehicle, stage and the next acta to fill (prefilled ?serie=&sitio=). New acta Prueba en sitio (prueba-sitio, repeatable: RTK fix in the monitor, report in the monitor and Wialon, coherent position, battery if it applies, photos). Rules: a unit counts toward its site goal only with a passed on-site test; «En operación» 7 days after a passed test without a fault (DIAS_OPERACION); a unit belongs to the site of its most recent acta. The installation acta now asks for the vehicle number, type and 12/24 V. Home per-site counts read the same endpoint (old count until the restart); site goal reads «1–2 unidades instaladas y probadas». Lote 2026-10-22_instalaciones points each site's install task at both actas. Crisis lote applied by Leo at 14:00; this deploy again needs restart actas-hbox before tablero.sh aplicar. Installation meeting (2026-10-22, 14:00; agreements confirmed by Leo at 16:13). Gemini recorded it in English, so what was said in Spanish was lost; Spanish notes in Leo's Drive (Google Meet → the meeting's folder) and the Juntas page now says to set the meeting language to Spanish before starting. Agreed: field owners ICAVE Alán, EIT Miguel, LCT Antonio, TIMSA Jesús Honorato (field technician and lead in Manzanillo); installation leads Alán and Daniel. Two Jesús: the site user jesus is Jesús Romero, the installation technician (his actas are signed that way); Miguel, Antonio and Honorato have no site account yet (t-alta-responsables-campo). D-22-1 decided: GO to the 5 + 5 pilot, but the order waits until the board's quick wins are done (t-v56-piloto blocked by them; the pilot's order and bench hitos are now dateless). Daily 15-min standup + weekly quick-wins / traffic-light review. LCT is handled separately: the material should be there; only the ironwork of the RTG brackets is missing (t-lct-herreria). Gibran opened the Wialon retranslator task during the meeting (T261022-5b37, Gibran + Jacobo, 26-oct); t-wialon-retranslator closed as its duplicate. Lote 2026-10-22_junta-instalacion; proyecto.json sites carry responsable, shown on the home page. FOTA over 4G — feasibility per board (2026-10-22, 16:30; Leo: «what's needed, is it feasible on every board?»). Yes on V5.6/V5.7 with no copper change: downlink = PIN_RTCM_TAP PC7 (USART6_RX ← R111 ← DOUT_4G, 115200), so Helgen's caster can interleave proprietary RTCM 3 frames (4001–4095) carrying signed image chunks that the F9P drops and the MCU collects; uplink = Modo B $PHLG (new fields appended); MODEM_EN/RST present. Yes on v6 natively (MCU owns the A7670SA: HTTPS via AT+HTTP*, HTTPREADFILE/CFTRANTX; must be designed into FW-3 with a non-transparent NTRIP socket; no K1 → the bootloader must self-revert). No on V3/V4/V5.5 (no MCU RX on the modem output; V5.5 PC7 NC, Blackpill has no PC7) → USB on visits; an experimental UBX-RXM-RTCM side channel (~75 B/s, unconfirmed) is test F0-d. Common design: bootloader A/B (sectors 0–1 boot, 2 metadata, 3 EEPROM moved from the last sector, 4–5 slot A 192 KB, 6–7 slot B 256 KB; fw 0.6.2 = 96 KB), two builds per release (build.flash_offset), SHA-256 + Ed25519 with the board ID in the manifest (covers D-08), trial boot with a server COMMIT (30 min or 3 resets → revert), one factory image via DFU, signing key never in the repo or on the server. By-products on V5.6/V5.7: remote $$$AS+X modem parameters with auto-revert, remote F9P CFG-VALSET. Never OTA: F9P firmware, the 4G NTRIP Master app (643 KB), the bootloader. Proposal D-22-6 (Leo decides): the factory image of the 108/322 and the 130 v6 carries bootloader + receiver and is not flashed until the FOTA 4 bench matrix passes; FOTA stays out of 0.7.0 (29-oct). Pieces F0–F4 ≈ 3 weeks (Claude, Gibran, Jesús). Open: caster software on HelgenSRV, per-unit NTRIP users, key custody, V4/V5.5 lifetime. Canonical: 02-Architecture-Software/2026-10-22_Drogheda_FOTA-por-4G_Factibilidad_ES_v1.0.md (site hardware/fota-4g-factibilidad/); figure 02-Architecture-Software/img/2026-10-22_Drogheda_FOTA-4G-Caminos-por-Tarjeta_v1.0.png (paths per board + common flash map); lote 2026-10-22_fota-4g. V5.6/V5.7 quick wins — T42a (2026-10-22, 17:00; Leo: «quick wins to make this board epic based on the audit files»). kicad/tools/t42a_v5_quickwins.py (dry run by default; --solo-bom; drift checks on every field, track and via; idempotent; keeps the pristine .T42abak) — applied: Leo chose D-22-7 (a) and ran it at 17:20; kicad 51a2cc6 with Rev6/Rev7 regenerated. BOM (sch + pcb identical, parity unchanged): D10 SMBJ33A → SMBJ33CA C83325 (Littelfuse; the audit's C8838 is not in JLC's DB and C2688178 had 39 pcs) · U15 MAX3232 → TRS3232E C308878 (pin-compatible, ±15 kV) · ten 22 µF C86817 (16 V, 4 144 in stock < 430 × 10) → C45783 (Basic, 25 V) · 10 nF C1589 → C57112 (Basic; the audit's P-6 had the direction backwards) · C22 label → 10uF/50V (C138687 is 10 µF) · 1 k → C21190, 22 k Rdfu1/Rig1/Rig2 → C31850 (1 %, 75 V), 49.9 Ω → C23185, D6 → C81598 (Basic) · 40.2 k → C12447, 68 pF → C28262 (Preferred). Copper (both boards): /IGN_IN (raw machine ignition, ≤ 1.3 mA through Rig1 22 k) 15 In1 segments 1.0 → 0.3 mm (min clearance on In1 0.15 → 0.54 mm); its via by Rig1 → (131.605, 54.75) + F.Cu stub 0.5 mm (0.15 → 0.30 mm, /NTC_CELL on In2); a 0.34-mm In1 stub keeps the P1-side via connected; V5.7 E-11: second /SYS5V via (146.365, 86.15) + 0.5-mm B.Cu stub (D12 → MCU LDO, C101 and U12 EN no longer hang on one via). Verified on the Mac (Python 3.14, byte-identical to the cloud; twice): DRC with refill + parity identical to the audit (3 MOD1 errors; 96 / 98 warnings; 0 unconnected; 13 PWR_FLAG); refilled shas b1313cd1 (V5.6) / 4e0a40f6 (V5.7); Gerber vs 13:00: masks, paste, silk, outline, NPTH identical, PTH 1 hole moved (+1 new on V5.7), copper changes only at the edits; BOM 226 / 229 parts in 107 / 115 rows. New finding (T42b): HV24 patterns 24V, IGN_IN, Q10_GATE lack the leading «/», so only /24V_IN is HV24; /24V, /IGN_IN, /Q10_GATE (+ V5.7 /VIN_FUSED, /SW_PWRIN, /BOOT_PWRIN; V5.6 /SW_FAN, /BST_FAN) are checked at 0.15 mm — not an electrical risk at ≤ 32 V (IPC 0.05–0.13 mm), but the team's 0.5-mm rule was never applied. Fixed patterns + the v6 DRU (F-01) give 28 / 27 clearance errors, 14 / 15 after T42a (V5.6: /24V near U2, /24V on In2, Cbst1, the IGN via; V5.7: /EN_PWRIN near /24V — U25 EN abs max 8.4 V —, 2 GND vias, the IGN via) → T42b by script before the 108/322. D-22-7 (Leo): (a) full T42a into the pilot (recommended, ≈ 40 min: script → kicad-cli refill + DRC → sha check → Fabrication Toolkit → commit) · (b) --solo-bom · (c) only D10. Canonical: 03-Architecture-Hardware/2026-10-22_Drogheda_Victorias-Rapidas_V5.6-V5.7_T42a_ES_v1.0.md (site hardware/v56-v57-victorias-rapidas-22oct/); figure img/2026-10-22_Drogheda_V5.6-V5.7-T42a_v1.0.png; test copies kicad/_to_delete/audit-20261022/qw/; lote 2026-10-22_t42a-v5. Designators in order — T43 (2026-10-22, evening; Leo: «designators … ordered connectors and resistors … I don't want to skip numbers … make sure the board reflects the version», D-22-8). kicad/tools/t43_renumber.py (plan / apply, backups *.T43bak; per-board rules for labels and rewritten/protected notes at the top) + kicad/tools/t43_check.py (token-by-token diff + --kicad: netlist through the table, ERC, DRC with parity and refill, before vs after). Standard prefixes only (C R D J U L Q F JP K MH MOD SW TP Y; Rcomp/Rfreq/Rig/RS… → R, Cbst/Ccomp/Cu → C, DB/Dbk/DzG/D4G1 → D, SW4G1 → SW), all connectors J (P*, J*, H4), no gaps. V5.6/V5.7 share numbering by V5.6 position (5-mm rows top→bottom, left→right): 235 shared parts (same symbol UUID, or C129/C130 added separately — now C59/C63) keep the same designator on both; board-only parts go last in their prefix (U15 = MP1584 fan buck on V5.6, TPS54360B on V5.7). v6 by its own position (parallel agent): 366/376 change. PWR_FLAG PF* → #FLG01… — KiCad counted the PF refs as real parts without footprint: those were the "normal" 13/13/19 parity errors → now 0. Labels: V5.6/V5.7 MODEM_EN_U7 → MODEM_EN_U13, Q10_GATE → Q6_GATE, Q6_BASE → Q5_BASE; v6 Q10_GATE → Q9_GATE, Q23_GATE → Q10_GATE (the name now means another net), Q22_BASE → Q2_BASE, Q6_BASE → Q4_BASE (HV24 patterns follow). DRU: V5.6 U2 → U15; V5.7 dead U2 exception removed; v6 U2/U20/U25 → U15/U4/U22. V5.7 silk «IGN 24V» → «IGN 12-24V»; title blocks dated 2026-10-22 + T43 comment; v6 title block now «EINARBoard HBOX v6» rev 6.0. Verified: netlist/ERC/DRC identical through the table, refill byte-identical, BOM/CPL identical part by part, Gerber geometry identical except F_Silkscreen. Commits: kicad e13d074 (V5.6/V5.7 + packages; made by the 18:00 projects-sync LaunchAgent, hence the generic message) and a08e49a (v6 + DRU single-pass fix). Open: D-22-9 (Leo) — designators are 0.5 mm with 0.1 mm stroke, below JLC's 0.8 / 0.15 minimum (recommended 1.0 / 0.2); proposal (a) pilot as is with the designator maps, (b) 0.8 / 0.15 in the T42b pass. Docs dated before 22-oct use the old numbering. Canonical: 03-Architecture-Hardware/2026-10-22_Drogheda_Designadores-T43_V5.6-V5.7-v6_ES_v1.0.md (site hardware/designadores-t43-22oct/) + CSVs 2026-10-22_Drogheda_T43_{V5.6-V5.7,v6}_viejo-nuevo.csv + maps img/2026-10-22_Drogheda_{V5.6,V5.7,v6}-Designadores-T43_v1.0.png; test copies kicad/_to_delete/audit-20261022/t43/ and t43-v6/; lote 2026-10-22_t43-designadores. 22–23-oct: living docs in T43 numbering, T44 silkscreen, one design document per board (Leo, 22-oct 18:56: "make sure that all documentation … has the correct reference on new designators, … an engineering document for each of the board … update the v6 designators"). Done by four agents overnight; the cloud container restarted twice, so integration slipped to 23-oct morning. Living docs (T43b): V5.6 datasheet + pinout (harness doc), pinmap-v6, manuals, site pages (producción/taller/descargas) and the board_v56.h comments (code identical) now use T43 designators; V5 bench procedures keep V5.5 numbering plus a V5.5→V5.6/V5.7 table; 54 dated docs got a banner (absolute link when the doc is not on the site); V5.5/V4/V3 untouched; 23 Project copies refreshed (parent d70dd80, firmware 18a9f82, kicad 2895871, hbox-docs 4c0b98c). T44 (kicad/tools/t44_serigrafia.py: dry run by default, --apply demands a byte-identical simulation, .T44bak; geometry from pcbnew, edits only (at)/(size)/(thickness)): silk designators 0.5/0.1 → 0.8/0.15 mm (JLC minimum) placed next to their own part, no part moved, no copper; .kicad_dru text ≥ 0.8/0.15 on F and B silk; .kicad_pro silk defaults 0.8/0.15 applied to footprint fields. D-22-9 = (b) on all three (v6: Leo 22-oct night; V5.6/V5.7: Leo 23-oct 08:53, pilot included). v6 bd27501: 338/350 placed, 12 left at 0.5 mm for Michelle (C44, C63, C101, C111, C112, R38, R58, R63, R64, R65, R98, TP6 + «IGN 12-24V»), DRC errors 11 unchanged, silk overlaps 17 → 4. V5.6 239/239 and V5.7 244/244 (93d13e3), DRC identical (3 MOD1), Rev6/Rev7 regenerated: only F_Silkscreen.gto changes (copper, masks, paste, drills, BOM, CPL identical). T44b (23-oct 09:15): 0.10 mm between texts let neighbours read as one word («R31R32R33»), so CL_TXT = 0.40 mm between a designator and any other text; V5.6/V5.7 re-run (44 more moved each, 0 leftovers, d19c832), Rev6/Rev7 regenerated again (only F_Silkscreen.gto); v6 waits for the layout close (would leave 17 instead of 12). Re-run T43 then T44 when the v6 layout closes; no hand placement of designators before that. Design documents: 03-Architecture-Hardware/2026-10-22_Drogheda_Documento-de-Diseno_{V5.6,V5.7,v6}_ES_v1.0.{md,pdf} + img/diseno-{V5.6,V5.7,v6}/ (site hardware/diseno-v56|v57|v6/, nav «Documentos de diseño»): 15 sections (ficha, changes, blocks, power tree, specs, MCU pins, connectors, schematic, PCB layers/3D/T43 map, test points, BOM, rules/DRC, risks/decisions, history, references), tables generated from the netlist, PCB and board_v56.h, plus the full schematic PDF. v6 plan rev 1.7. Lote 2026-10-23_t44-documentos-diseno (closes d-22-9 and t-docs-designadores-t43; creates the bench-procedure/forms task for 0.7.0). Lessons: device_commit_files leaves files 600/700 → chmod 644 before publishing; long agent runs must checkpoint to a PROGRESS file (results survived the restarts in the work dir and transcripts). Canonical: 03-Architecture-Hardware/2026-10-22_Drogheda_v6-T44-Serigrafia_ES_v1.0.md (site hardware/v6-t44-serigrafia/).

1. System architecture (corrected from the BOM, 2026-06-20)

 Machine power+ignition (12/24/48/110/230 V, per equipment)
   │
   ▼  ┌──────────────── Gabinete IP67 (ABS, Yetlebox P3901) ─────────────────┐
 breaker│ Phoenix SPD · fuse holder · DIN rail · SSR/opto (ignition isolation)│
 + SPD ►│ Mean Well DDR-60G-24 ──► regulated 24 Vdc ───┐                       │
        │                                              │  GX16-5 connector     │
        │   ┌────────── HBOX (3D-printed ASA) ─────────┼────┐                  │
        │   │ Mean Well SD-15B-05 (18–36V→5V,3A) ──► 5V rail │                 │
        │   │   ├► PowerBoost 1000C (+18650 Li-ion 1S4P) backup                │
        │   │   ├► STM32F411 Blackpill WATCHDOG ──UART(PA2)──► simpleRTK2B Pro  │
        │   │   │     └ switches RTK 5V via 2N3904→IRF9540N (PA1)              │
        │   │   ├► simpleRTK2B Pro (ZED-F9P) + 4G NTRIP Master (XBee LTE)      │
        │   │   └► ignition 24V ──► DFR1015 buck ──► STM32 PA5 (ign sense)     │
        │   └──────────────────────────────────────────────────────────────┘ │
        └───────────────────────────────────────────────────────────────────┘
            4G/LTE ▲ RTCM3 in (NTRIP)        │ NMEA out (UDP)
   Base station (Ardusimple AS-PRO-CORS) ────┘        ▼
            retranslator.py ─(anti-jump+speed filter)─► Wialon / Traccar ─► VERONICA

Power into HBOX = clean 24 V from the cabinet (via GX16-5). Internal Mean Well SD-15B-05 makes 5 V; PowerBoost 1000C + 18650 is battery backup; DFR1015 conditions ignition to the Blackpill. (This diagram is the field as-built; the EinarBoard 1.0 carrier supersedes the battery + ignition path — LTC4040 battery-backup on-board, DFR1015 removed entirely (Rev 1.1): GX16 pin 3 raw ignition → 22k/10k divider + BAT54 clamp → PA5. See 03-Architecture-Hardware/watchdog-electrical-design-state.md + the 2026-07-06 audit.)
Corrections arrive over the 4G modem (RTCM3 via NTRIP), not the GNSS — so a GNSS reset can't fix a dead link; recover by power-cycling the stack (v2 does).
Watchdog = STM32F411; see 03-Architecture-Hardware/watchdog-schematic.

1b. Canonical invariants (inherits `Helgen Project Ethos`)

The rules this system must never violate. Check every design/code output against these before presenting; if it breaks one, say so and propose the compliant fix.

Power-off is the safe state. The RTK stack defaults OFF (gate pull-up) until the MCU asserts; loss of confidence → safe state, not best-guess.
Never vanish, never loop. A unit must keep reporting (standalone if needed) rather than go silent, and must never enter an infinite fast-reboot loop.
Corrections ride the 4G modem, not the GNSS — recover the link by power-cycling the stack; a GNSS reset is never a fix for lost NTRIP.
No material that softens below ~80 °C (PLA-class) in the thermal path — the current ASA enclosure complies. Design to the measured cabinet-interior temperature, not spec-sheet ambient.
Backend reads/forwards without head-of-line blocking, and the anti-jump filter must never permanently lock out a healthy unit.
No secrets in the repo — ever. (The committed MSSQL password is a live violation to remediate.)

1c. Hard constraints (non-negotiables)

HBOX input is the cabinet's regulated 24 V + isolated ignition; don't re-implement the cabinet's surge/breaker/SSR on the HBOX.
IP67 maintained — cooling by conduction only; no IP-breaking vents/fans.
Bench-test firmware before any field flash (no STM32 build in the sandbox).
Client-facing docs are Spanish, routed through Leo.
Use the file tools for file changes; verify the shell mount before bulk moves.

2. Directory (Helgen English `NN-` standard — keep this table current)

Folder	Holds	Key files
`00-Project-Management`	plan, ethos, hackathon, financials, handover, client comms, Drive tooling	00-Project-Management/PLAN · 00-Project-Management/Engineering-Handover · `ethos.md` · `hackathon-plan.md` · `Financials.md` · `Drive-Upload/` · `client-comms/`
`01-Requirements`	what we build	`SRS.md` · `HBOX-product-spec.md`
`02-Architecture-Software`	backend/software analysis, ADRs	`backend-review.md` · `2026-10-22_Drogheda_FOTA-por-4G_Factibilidad_ES_v1.0.md` (FOTA over 4G per board; D-22-6)
`03-Architecture-Hardware`	HBOX/cabinet, wiring, BOM, watchdog PCB v3	`hardware-respec-and-pcb-brief.md` · `cabinet-electrical-bom.md` · `watchdog-schematic.md` · `watchdog-health-telemetry.md` · `firmware-review.md` · `BOM-master.md` (+§5 Block B/E/H/I parts) · `watchdog-pcb-v3-design.md` (schematic spec) · `watchdog-pcb-v3-bom.xlsx` · `watchdog-pcb-v3-kicad-guide.md` (KiCad→JLCPCB) · `watchdog-pcb-v3-blockdiagram.svg` · `watchdog-protoboard-bringup.md` + `watchdog-proto-bench-bringup-v3.md` · `watchdog-connections.xlsx` (PCB pin/net list; H1 DNP; +B/H/I rows) · `watchdog-connections-rationale.md` (+§7 additions 2026-07-02) · `watchdog-electrical-design-state.md` (CANONICAL — read first) · `watchdog-production-schematic-delta.md` (PROD build spec; LTC4040 §4 values) · `kicad/` — `hbox-watchdog-v3.kicad_sch` (DEV/proto) · `hbox-watchdog-v3-PROD.kicad_sch/.kicad_pcb` (PRODUCTION: ERC 0, layout started, DRC baseline) · `Drogheda-sym.kicad_sym` (MP1584EN · LTC4040EUFD · AO4406A) · `Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx` (proto assumptions ledger) · `Guia-Conexion-Protoboard/` (LaTeX source; `modulos-pinout.tex` = visual parts catalog) → `Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf` · `2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md` (XBee 2.0 mm bridge + cheap-4G survey) · `circuitikz-wiring/` (sheet + Beamer v2.1, blocks 1–11; XBee-socket 3V3 fix 07-08; `Drogheda_Diagrama-Unico-Proto` = todo-en-una-hoja para verificación rápida, Modo B; v1.1 07-10 agrega XBee 20-pin obligatorios VREF(14)→VCC · ON/OFF(20)→GND · GND×4 + USB config + franja de pinouts para el técnico; HiRes-300dpi.png para TV; v1.2 07-20: letras G/D/S·B/C/E en todos los transistores + bloque 5b Q10+DzG 15V) · Guía v3.1 (5b Q10+Zener · 9c pines obligatorios XBee + USB · disipadores · plano 10×10) · lista de compras reconstruida DESDE CERO (1 tarjeta ≈MX$2,087) · `watchdog-protoboard-BOM-3boards.xlsx` + `watchdog-LISTA-DE-COMPRAS-ES.xlsx` (proto BOMs; 07-10: +BOB-08276/PRT-08272, buck «MODEM 3.3V», breakout USB-C+cable, botón/LED módem, straps VREF/ON-OFF, surtido +220R/22k) · `2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md` (CLOSED — Rev 1.1 fixes) · `Assembly-BOM-Split.md` + `LCSC-search-list.md` (verified LCSC) + `JLCPCB-Order-Guide.md` (ordering runbook) · `harness-connector-pinout.md` + `Socket-Pinout-Silkscreen.md` · `EinarBoard-Manual/` (Rev 1.1 order-prep pack: `einarboard-manual.tex` → branded PDF · `helgen_einarboard_1.0_production_bom.xlsx` · `tools/generate_production_bom.py` + `tools/sync_bom.py` Excel→LaTeX BOM sync) — plus repo-root `scripts/prep_order_release.sh` (safe cleanup + release commit) · `2026-10-16_Drogheda_Auditoria-Produccion_V5.6-V5.7-v6_ES_v1.0.md` (production audit + comparison table) + `2026-10-16_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-3_ES.md` · `kicad/tools/t25_mounting_holes_v55.py` (restores the 7 V5.5 holes) · `kicad/tools/t27_paso1_2_mh11_rs1_kelvin.py` (MH11 out + RS1 Kelvin, V5.6/V5.7) · `kicad/tools/t28_v6_mecanicos.py` (v6: U25 part code, stackup, U6 paste) · `kicad/tools/t30_v56_v57_mecanicos.py` (V5.6/V5.7 mechanical fixes, 19-oct) · `kicad/tools/t31_c129_vsys_quitar_dbk2.py` (V5.6/V5.7 schematic: C129 at U6 VSYS + Dbk2 out, 20-oct) · `kicad/tools/t32_c130_vin_u7.py` (V5.6/V5.7 schematic: C130 at U7 VIN, 21-oct) · `kicad/tools/t33_v56_v57_auditoria_21oct.py` (V5.6/V5.7 PCB fixes from the 21-oct audit) · `kicad/tools/t34_v56_pasada6.py` + `t35_v56_via_u7.py` (V5.6 pass 6) · `kicad/tools/t36_v57_pasada6.py` + `t37_v57_c129_gnd.py` (V5.7 pass 6) · `kicad/tools/t38_v6_courtyards_mh.py` (v6: courtyards of the 11 easyeda2kicad footprints + library, MH6 `/3V3` to B.Cu, 4-mm MH rule in the `.kicad_dru`) · `kicad/tools/t39_v6_bloque_a.py` (v6 block A, proposal α: D34/L22/R53/R54 moved, SW + VEH5V tracks, In1/In2 cleared, MH8 free) · `kicad/tools/t40_v6_mh4.py` (v6 MH4 free: D23/D24 moved, SIM_CLK via In1, SIM_RST above D25, NTC around the hole, TVS + U19.92/94 GND vias) · `kicad/tools/t42a_v5_quickwins.py` (V5.6/V5.7 quick wins T42a: BOM with stock for 430, /IGN_IN 0.3 mm on In1, V5.7 E-11 via; `--solo-bom`) · `2026-10-16_Drogheda_Auditoria-Produccion_v6_ES_v1.0.md` + `2026-10-16_Drogheda_Plan-Fines-de-Semana_v6-Produccion_ES.md` (v6 audit + weekend plan, rev 1.5) · `2026-10-19_Drogheda_Re-Auditoria_V5.6-V5.7-v6_ES_v1.0.md` (re-audit of all three) + `2026-10-19_Drogheda_Instrucciones-Michelle_V5.6-V5.7-Pasada-4_ES.md` · `2026-10-19_Drogheda_V5.6_Clasificacion-Criticos_ES_v1.0.md` (V5.6 critical vs. can-stay; C129) · `2026-10-21_Drogheda_Auditoria-Pasada-4_V5.6-V5.7_ES_v1.0.md` (audit of pass 4, T32/T33 results, pass-5 review, pass 6 done by Claude with T34–T37 + D-21-2) · `2026-10-21_Drogheda_Estado-v6-T25-T28_ES_v1.0.md` (v6 state, rev 1.3 of 22-oct: T25 + T28 + T38 + T39 block A + T40 MH4 applied, MH rule, D-22-4; figures `img/2026-10-22_Drogheda_v6-T39-Bloque-A_v1.0.png` + `img/2026-10-22_Drogheda_v6-T40-MH4_v1.0.png`) · `2026-10-22_Drogheda_Auditoria-Final-Produccion_V5.6-V5.7_ES_v1.0.md` (FINAL production audit of the V5.6/V5.7 fab packages: GO pilot 5 + 5 with 3 order conditions, NO-GO 108/322 until bench with 0.7.0; 30 findings, 16 risks) + `…_Protocolo_ES_v1.0.md` (the audit protocol / "reprompt") + `Auditoria-Final-V56-V57/` (LaTeX sources → 33-pp PDF + 19-frame Beamer; `fig/`; `scripts/` gerb.py · gcmp.py · netparse.py · copper.py · riesgos.py) · `img/2026-10-22_Drogheda_.png` (8 figures) · `2026-10-22_Drogheda_Victorias-Rapidas_V5.6-V5.7_T42a_ES_v1.0.md`* (quick wins T42a + HV24 netclass finding → T42b + D-22-7; figure `img/2026-10-22_Drogheda_V5.6-V5.7-T42a_v1.0.png`) · `2026-10-22_Drogheda_Designadores-T43_V5.6-V5.7-v6_ES_v1.0.md` (T43 designators in order on V5.6/V5.7/v6 + D-22-9; old→new CSVs `2026-10-22_Drogheda_T43__viejo-nuevo.csv`; maps `img/2026-10-22_Drogheda_-Designadores-T43_v1.0.png`) · `kicad/tools/t43_renumber.py` + `t43_check.py` + `fab_package.py` (headless Fabrication Toolkit) · `2026-10-22_Drogheda_Documento-de-Diseno_{V5.6,V5.7,v6}_ES_v1.0.md/.pdf` (one design document per board; images + full schematic PDF in `img/diseno-*`) · `2026-10-22_Drogheda_v6-T44-Serigrafia_ES_v1.0.md` + `kicad/tools/t44_serigrafia.py` (silk designators 0.8/0.15 by script on all three; `t44_drc.py`, `t44_diff.py`, `t44_export.py`)
`04-Source-Code`	firmware + backend repos	`firmware/` (own git repo `hbox-firmware`: `blackpillrtkcode_v2/` deploy · `legacy/` v1 · `docs/LOGGING-SPEC.md` v2.1 · `hbox_v5_bringup/board_v56.h` (V5.6/V5.7 pin map, 22-oct; 0.7.0 base)) · `htracker/` · `notifications/` · `rtk-config/`
`05-Analytics-Reports`	SQL views, dashboards (VERONICA/PowerBI), observability	`2026-06-22_Drogheda_Manual-Logs-Grafana_v1.0.pdf` (Grafana/Loki log-consultation manual)
`06-Testing-Validation`	RCA, diagnostics, test evidence, log analysis & tooling	`RCA-2026-06-field-failures.md` · `remote-diagnostic-protocol.md` · `2026-06-20_Drogheda_Bench-Log-Analysis_v1.0.md` (rev-3) · `2026-06-20_Drogheda_GNSS-Findings-Summary.md` · `log-analysis/` (repo `hbox-log-tools`: `log-explorer.html` · `analyze_logs.py` · `build_dashboard.py` · `docs/manual.pdf`)
`Marketing`	product-facing collateral (LaTeX→PDF)	`HBOX-Datasheet/` (industrial spec sheet) · `HBOX-Brochure-RTK/` (flyer)
`99-Archive`	superseded raw inputs (read-only)	`situation_ORIGINAL.md`
`hbox-docs/`	the command centre (submodule): internal site drogheda.helgen.online — MkDocs + Flask backend (actas, pendientes, inventario, sitios, equipo, enfoque, actividad)	`CLAUDE.md` (where each piece lives) · `docs/datos/proyecto.json` (Ruta, hitos) · `docs/hardware/index.md` · `docs/tableros/ingenieria.md` (decisions) · `docs/bitacora.md` · `scripts/sync-docs.sh` (publication policy) · `scripts/deploy.sh` · `scripts/tablero.sh` + `backend/tablero.py` + `backend/lotes/` (board snapshot and Claude's lotes, 21-oct) · `_estado/` (snapshot, gitignored) · `DESPLIEGUE.md`
`.claude/skills/`	vendored project skill	`project-drogheda/`

Structure follows the Helgen Project Template (English NN-). The Google Drive mirror keeps the legacy Spanish 00_…99_ scheme (Drive manual); finalized deliverables export there. Naming: AAAA-MM-DD_Drogheda_Descripción_vX.X — no loose files in root except this index. Empty legacy Spanish dirs remain (the mount can't delete them) — remove locally: rmdir 0?_* 99_Archivo docs hardware …

3. HBOX BOM (per unit, 24 V variant — see `03-Architecture-Hardware/BOM-master`)

simpleRTK2B Pro (AS-RTK2B-PROF9P-L1L2-NH-00) · 4G NTRIP Master (AS-XBEE-4G-NA-UFL-00) · Blackpill STM32F411 · U-blox multiband antenna (AS-ANT2B-ANN-L1L2-50SMA) + 2× LTE antennas (AR1582) · Mean Well SD-15B-05 (24→5 V) · PowerBoost 1000C + 18650 1S4P · DFR1015 (ignition) · 2N3904 + IRF9540N + 2N7000 watchdog · GX16-5 HBOX↔cabinet · ASA case/top/ brackets · Telcel micro-SIM.

4. Deployment & people

BUs / terminals: ICAVE (stress lab, live), TIMSA, EIT, LCT. ICAVE machine voltages: RTG 24 V, Reach Stacker 24 V, Empty Handler 24 V, Tractoplana 12 V, Montacargas 12 V. Target: 30 units by August.

Name	Email	Role
Leo Rodriguez	leo@helgen.tech / ceo@helgen.tech	Helgen — founder/CEO
Adriana Del Angel	adriana@helgen.tech	Helgen — implementation/plan
Paola Rodriguez	paola@helgen.tech	Helgen
Angel Daniel Martinez	daniel@helgen.tech	Helgen
Gibran Ortega	gibran@helgen.tech	Helgen — GPS/telemetry
Agustín Alfonseca	alfonseca.agustin@icave.com.mx	Client — ICAVE Tech Research Supervisor
Leon David Piña	pina.david@hutchisonports.com.mx	Hutchison Ports

5. Where things live (off this workspace)

Google Drive (team source of truth): Drogheda (GPS RTK) — official numbered structure 00–99 + manual LEEME_Drogheda_Estructura_y_Uso. Mirror this workspace's structure to it for finalized deliverables.
Second Brain vault (~/Documents/Second Brain/03 Projects/Helgen/): only polished, evergreen notes (decisions, lessons, contacts) — see Project-Drogheda/ once synced.
Backend repo: ssh://git.helgen.dev:6611/htracker (retranslator + monitor), cloned at 04-Source-Code/htracker (branch feature/test500unidades).
Observability (logs): backend logs ship off-box to Grafana Loki (free tier, 50 GB/mo, 14-day) via Vector (default) or Grafana Alloy reading journald (capped 200 MB) — 04-Source-Code/htracker/log-shipping/ (README.md runbook · setup-logging.sh · vector.toml). Read in Grafana → Explore → Loki: {job="htracker"} (Vector) or {unit="htracker.service"} (Alloy). Consultation manual (PDF): 05-Analytics-Reports/2026-06-22_Drogheda_Manual-Logs-Grafana_v1.0.pdf. Creds in /etc/vector/htracker.env (server) — never in the repo.
Firmware repo: ssh://git.helgen.dev:6611/hbox-firmware (STM32F411 watchdog), lives at 04-Source-Code/firmware (branch main) — its own git repo with README, docs/PINOUT.md, redacted RTK-config template, CHANGELOG. Push instructions in its README. v2.1 logging spec at docs/LOGGING-SPEC.md (structured/parseable Blackpill log; not yet flashed).
Log-tools repo: ssh://git.helgen.dev:6611/hbox-log-tools (HBOX log analysis — in-browser Log Explorer + batch analyzer + dashboard + Spanish LaTeX manual), lives at 06-Testing-Validation/log-analysis/. Raw logs + config files git-ignored (credentials). Built 2026-06-20.
Project tracker: drogheda.helgen.online → Pendientes (since 13/14-oct; the Notion task tracker and the HBOX Unit Status — Bench Triage board are historical, imported once) + Mattermost (team chat). Claude changes the board only through lotes (★ above).

6. Hard facts — don't relearn these

NMEA GGA quality ≥4 = healthy (4 = RTK-fixed, 5 = RTK-float).
Designators were renumbered on 2026-10-22 (T43) on V5.6, V5.7 and v6 (standard prefixes, all connectors J, no gaps; V5.6/V5.7 share numbering). Anything dated earlier uses the old refs → old→new table in 03-Architecture-Hardware/2026-10-22_Drogheda_Designadores-T43_V5.6-V5.7-v6_ES_v1.0.md. V5.5 as-fabbed boards keep their old silk. Power flags must be #FLG… (a PF1 ref makes KiCad count it as a part without footprint).
com.leo.projects-sync (LaunchAgent, daily 18:00) auto-commits and pushes every project repo («auto-sync …»; it committed T43 for V5.6/V5.7 as e13d074): never leave half-applied changes in a repo across 18:00 (D-19-3, keep kicad/ out of it, is still open).
ZED-F9P rated −40…+85 °C — heat casualties are the 18650/PowerBoost and the 4G modem, not the GNSS or the case.
The case is ASA (UV-stable, softens ~95–100 °C) — adequate for the nested ABS IP67 cabinet interior; the enclosure is not the liability. A bare fan inside a sealed box does not cool it — conduct heat out, or use a ducted fan (v3.0). See hardware brief §2b.
Corrections come over 4G → recover by power-cycling the stack (v2), not a GNSS reset. Backend can take healthy units off Wialon (HOL block + anti-jump lockout).
HBOX input = 24 V from the cabinet; design the redesign around that.
Firmware: edit 04-Source-Code/firmware/blackpillrtkcode_v2/blackpillrtkcode_v2.ino (own git repo hbox-firmware); bench-test before field flash (sandbox can't build STM32).
20 Jun logs — receivers are fine; RTK is not being achieved. Every board emits valid NMEA (good sats/HDOP) but every epoch is SPS (1), zero RTK (4/5). Corrections aren't applied: free public rtk2go caster (no SLA), F9P config dumped from RAM only (verify saved to FLASH; check the Pro's XBEE↔UART2 switch), plus indoor sky. F9P message config is correct (GGA on UART2 @1 Hz).
The 4G-NTRIP-Master console does NOT prove forwarding — a healthy unit logs the same sparse console ("registered", no State main/UDP Bytes sent) as a failed-looking one. Confirm health only from a .ubx (fix), the Blackpill, or a server delivery capture. → "master-14 ingest fault" RETRACTED; only master 21 (modem 0xFFFFF + 511 AT errors) is a confirmed fault.
Healthy GNSS baseline = RTK14NTRIP14_440 (server-verified 1 Hz delivery, 12 sats, HDOP 0.75, but SPS not RTK). Raise the bar to an open-sky fix-≥4 capture.
Heat is NOT implicated by the bench logs (faults reproduce cold; v1 has no thermal channel). Field thermal hypothesis still needs a thermocouple cabinet soak.
dashboard.html predates the rev-3 retraction (still marks the no-forward captures "Failed"); the canonical corrected record is the GNSS summary + the rev-3 findings doc.

7. Working notes

Use the file tools (Read/Write/Edit) for file changes; the shell mount can go stale — verify before bulk shell moves. Six empty legacy dirs (docs, firmware, …) remain from the restructure; delete them manually.
Client-facing docs are Spanish and route through Leo.

Objectivity — partner, not sycophant

I want an objective partner, not a sycophant. On every task:

Genuine take first. Lead with your real assessment. Don't mirror my tone or sentiment, and don't open by validating me.
Disagree when you disagree. Say so plainly and explain why — and pair the criticism with a concrete better option (direct and constructive).
Self-check. If a reply is about to start with something semantically like "You're right" / "Good point" / "Great question," stop and first answer: "Is this true?"

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