| title |
project |
date |
tags |
| HBOX Watchdog v3 PROD — Socket Pinouts (for silkscreen) |
Project Drogheda |
2026-07-05 |
| project-drogheda |
| hardware |
| pcb |
| silkscreen |
| pinout |
|
Socket pinouts — for silkscreen labelling
Connected pins only (NC pins omitted). "Silk" = suggested short label that fits the
2.54 mm pitch (vertical text). Pin 1 is the square pad on each header.
J1 — Blackpill (left row, pins 1→20 left to right)
| Pin |
Net |
Silk |
| 5 |
NRST |
NRST |
| 6 |
BAT_SENSE |
BSNS |
| 7 |
PWR_CTRL |
PCTL |
| 8 |
GNSS_TX |
G-TX |
| 9 |
GNSS_RX |
G-RX |
| 10 |
5V_SENSE |
5VS |
| 11 |
IGN_SENSE |
IGN |
| 12 |
FAN_PWM |
FPWM |
| 14 |
EXT_LED |
ELED |
| 15 |
NTC_TEMP |
NTC |
| 17 |
FAN_TACH |
FTAC |
| 18 |
3V3 |
3V3 |
| 19 |
GND |
GND |
| 20 |
SYS5V |
5V |
J2 — Blackpill (right row, pins 1→20)
| Pin |
Net |
Silk |
| 1 |
BATLED1 |
BL1 |
| 2 |
BATLED2 |
BL2 |
| 3 |
BATLED3 |
BL3 |
| 4 |
BATLED4 |
BL4 |
| 5 |
CHRG_EN |
CHEN |
| 6 |
USART1_TX |
U-TX |
| 7 |
USART1_RX |
U-RX |
| 11 |
CHRG_STAT |
CSTA |
| 12 |
CHRG_FAULT |
CFLT |
| 13 |
BYP_CTRL |
BYP |
| 14 |
I2C_SCL |
SCL |
| 15 |
I2C_SDA |
SDA |
| 18 |
SYS5V |
5V |
| 19 |
GND |
GND |
| 20 |
3V3 |
3V3 |
J7 — 4G XBee row 1 (pins 1→10 top to bottom)
| Pin |
Net |
Silk |
| 1 |
3V3_MODEM |
3V3 |
| 2 |
DOUT_4G |
DOUT |
| 3 |
DIN_4G |
DIN |
| 10 |
GND |
GND |
J8 — 4G XBee row 2
All pins NC — no labels needed.
| Pin |
Net |
Silk |
| 2 |
3V3 |
3V3 |
| 5 |
SW_5V |
5V |
| 6, 7 |
GND |
GND |
| 15 |
GNSS_RX |
G-RX |
| 16 |
GNSS_TX |
G-TX |
| 17 |
DOUT_4G |
DOUT |
| 23 |
USART1_RX |
U-RX |
| 29 |
GND |
GND |
Anchor labels I already staged (power/ground, if you want to keep the placement):
J1: 3V3 / GND / 5V at pins 18-20 · J2: same at pins 18-20 · J7: 3V3 (pin 1), GND (pin 10) ·
MOD1: 3V3 (pin 2), 5V (pin 5), GND (pin 6/7). They're in my memory only — not saved — so
just re-create them from this table in KiCad.
