125 lines
8.0 KiB
Markdown
125 lines
8.0 KiB
Markdown
---
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title: Watchdog v3 PROD — PCB Routing Status
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tags: [project-drogheda, hardware, pcb, kicad, routing, freerouting, status]
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project: Project Drogheda
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author: Helgen CTO
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date: 2026-07-03
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status: Active — routing skeleton complete (98%), punch-list to fab-ready below
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---
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# HBOX Watchdog v3 PROD — Routing Status (2026-07-03)
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Board: `kicad/hbox-watchdog-v3-PROD.kicad_pcb` — 120×100 mm, 126 footprints.
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Continues the routing Fable started (and left broken by a mid-route spend-limit cutoff).
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## ⭐ UPDATE 2026-07-03 — RESPUN TO 4-LAYER (the real fix)
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The 2-layer board **could not take wide power**: FreeRouting left **51 unrouted** even at a
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moderate 1.0/0.8 mm (and the intended 1.5+ mm was worse). That's the honest limit of 2 layers
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on a board this dense (3 switchers + 4G modem + RTK shield). **Leo's call: respin 4-layer.**
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- **Stackup now 4-layer:** `F.Cu / In1.Cu (GND plane) / In2.Cu / B.Cu` (JLC standard 1.6 mm; no
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explicit stackup block → JLC applies theirs). Converted by adding In1.Cu(id 4)+In2.Cu(id 6) as
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copper (KiCad 9 IDs verified empirically; hand-`add_layer` cascades junk — direct file edit used).
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- **GND moved to the In1 inner plane** (pour relayered B.Cu→In1.Cu, refilled). Exports as
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`(plane GND (polygon In1.Cu …))` → FreeRouting bonds GND to the plane; routes on F/In2/B.
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- **2-layer routing stripped** for a clean 4-layer route.
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- **Route artifact for Leo:** `kicad/hbox-watchdog-v3-PROD-4layer-wideclass.dsn` (PWR_HI 1.5 mm,
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PWR_MID 1.0 mm, signals 0.2 mm, through-via `Via[0-3]`, 4 routing layers). Run FreeRouting on the
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Mac → `.ses` → I import + refill In1 plane + DRC. Instructions: `kicad/RUN-4layer-autoroute-README.md`.
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- **Order at JLC as 4-layer.** Wide power now has room; solid GND is the reliability win we went for.
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- Backups: `…bak-pre4layer-*` (2-layer routed), `…bak-pre4Lroute-*` (4-layer pre-strip).
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### 4-layer route imported (FreeRouting, 70 passes)
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Leo ran FreeRouting on `…-4layer-wideclass.dsn` → **13 unrouted** (vs **51** on 2-layer — the
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respin worked). SES imported: **862 tracks, 129 vias**, In1 GND plane filled (8,550 mm²),
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**no new shorts** (the 5 shorting-item lines = placement baseline: J7↔MOD1 no-net under the
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shield ×4 layers + SYS5V↔SW_5V kiss). **Wide power rails routed with real width** — the goal.
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**Punch-list (finish in KiCad interactive router — fine-pitch, needs eyes; quick on 4-layer):**
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- **~7 IC-pad opens, all in the U3/U6 cluster (center):** `BAT_PLUS` (U6.23), `VIN_SW` (Q7.5↔U6.7),
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`IGATE` (Q7.4↔U6.15), `SW_5V` (C3.1↔Q1.3), `3V3` (→U3.3), `I2C_SDA` (U3.1↔R31.2), `I2C_SCL` (U3.2).
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U3 = SHT40 (0.3–0.5 mm pads), U6 = LTC4040 QFN — the autorouter can't finesse these.
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- **~10 GND pads not fully bonded to the In1 plane:** THT — P10.2, P13.3, J1.19, J2.19, MOD1.6, J7.10
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(fix: set In1 zone pad-connect to solid, or add a plane via); SMD — C7.2, C11.2, Rfreq.2, U3.4
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(fix: short GND via to In1). Safe to do via MCP (GND-to-GND).
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- Minor: FreeRouting parked short `BAT_PLUS`/`SW_5V` segments **on the In1 plane layer** — reroute
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onto F/In2/B for a fully solid plane (cosmetic-ish for this slow board).
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> The 2-layer material below is retained for history; the board is now 4-layer.
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## What was done this session
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1. **Ripped up Fable's partial hand-route.** It was interrupted mid-route with **19 net-to-net
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shorts** (GND↔SYS5V, MAIN5V↔VIN_SW, 24V↔Q10_GATE…), 6 track crossings, 13 dangling vias —
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not salvageable. Stripped all routed copper (178 segments + 32 vias) back to clean placement;
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footprints, nets, and the B.Cu GND pour preserved. Backups kept (see below).
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2. **Net-classes / rules.** Global clearance was **0 → fixed to 0.2 mm** (would have let the
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router short). Project already carried `PWR_HI`/`PWR_MID` patterns (kept: PWR_HI = BAT_PLUS,
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SW_BAT, MAIN5V, VEH5V, SYS5V, VIN_SW; PWR_MID = SW_5V, 3V3_MODEM, 5V_FAN, 24V, 24V_IN, IGN_IN,
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SW_FAN, SW3_NODE, FAN_RET).
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3. **Autorouted with FreeRouting 1.9** (best-of-N, on the Mac's Java 23). Result imported:
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**1072 segments, 131 vias, 100 % of nets routed** (0 unrouted at import), and — critically —
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**no new shorts or clearance violations from the routing itself**.
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4. **GND handled as a plane.** The B.Cu GND pour exports as a real `(plane GND)`, so FreeRouting
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bonded GND to the bottom plane instead of thin traces. Pour **filled** (8160 mm²).
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## Current DRC = 204 (down from Fable's 276)
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Essentially the **placement baseline** + connectivity stragglers:
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| Bucket | Count | Nature |
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|---|---|---|
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| courtyards_overlap | 67 | **by-design** under-shield overlap (MOD1/J7/J8) — pre-existing |
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| silk_overlap / silk_over_copper | 59 / 50 | cosmetic silkscreen — pre-existing |
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| pth_inside_courtyard, lib_footprint, hole_to_hole, solder_mask | 9/4/1/3 | placement baseline |
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| clearance | 7 | sub-mm placement **pad kisses** — pre-existing (in Fable's Jul-2 baseline) |
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| shorting_items | 3 | **placement, not routing**: J7-Pin8↔MOD1-A5 (no-net, under shield) ×2; **SYS5V↔SW_5V pad kiss** — verify (real nets) |
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| starved_thermal | 1 | one GND thermal relief with 1 spoke — trivial |
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| **unconnected_items** | **17** | **the routing punch-list ↓** |
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## Punch-list to fab-ready (the last 2 %)
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**A. Close 17 open connections (do in KiCad GUI — interactive route with copper visible; NOT
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blind by coordinate, which is how the 19 shorts happened last time):**
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- **U3 (SHT40) — 4 pins near-missed**: pad1 SDA (65.3, 77.6), pad2 SCL (65.3, 78.4),
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pad3 3V3 (66.7, 78.4), pad4 GND (66.7, 77.6). Tiny 0.5×0.3 mm pads on 0.8 mm pitch; the
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I2C/3V3 tracks stop ~3–5 mm east near U4. **Functionally critical** (sensor won't work).
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- **~13 GND-to-plane**: edge THT grounds not reaching the plane — P5 pad2 (20.5, 6),
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H3 pad3 (31, 11), P13 pad3 (41, 6), MOD1 pad6 (72.7, 48), J1 pin19 (72.7, 16),
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J2 pin19 (72.7, 33.8) — plus a few GND track/via gaps mid-board. Fix by nudging the zone /
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short GND jumper to the plane body (visible in GUI).
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**B. Widen power nets to class widths.** The autoroute ran at a **uniform 0.2 mm** (see tooling
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note) — power rails are currently thin. Widen to spec: **PWR_HI ≥1.5 mm, PWR_MID/SW_5V ≥0.8–1.0 mm,
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signals 0.25 mm** (per `watchdog-pcb-v3-kicad-guide` §6: power/5V ≥0.5, SW_5V ≥0.8). Easiest via
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GUI: select each power net → set width from net-class → push-and-shove reflows neighbors.
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**This is the project's core reliability lever (voltage drop / heat) — required before fab.**
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**C. Verify the SYS5V↔SW_5V placement kiss** (bottom-right cutoff-switch area) — real nets.
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## Tooling notes (why power isn't already wide)
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- FreeRouting 1.9 jar needs **Java 17+**; the analysis sandbox only has Java 11 (no net to fetch a
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JDK) → can't run the jar there. The Mac has Java 23.
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- The KiCad-MCP `export_dsn` (swig backend) **flattens all nets into one `kicad_default` class at
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0.2 mm** — it does not apply the `PWR_HI/PWR_MID` patterns. So the MCP autoroute (which
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re-exports internally) routes everything at 0.2 mm; the wide classes can't be driven through it.
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- MCP tool calls cap at 30 s, but FreeRouting finishes **asynchronously on the Mac** (~2–3 min) and
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the SES still imports — that's how this route landed despite a "timeout".
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- **Path to wide-power autoroute (optional):** inject `PWR_HI/PWR_MID` classes into the exported
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DSN and run `java -jar freerouting-1.9.0.jar -de <fixed>.dsn -do out.ses` on the Mac, then
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`import_ses`. Otherwise just widen in the GUI (recommended — current signal routing is good).
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## Backups (in `kicad/`)
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- `…kicad_pcb.bak-preAutoroute-20260703-200734` — clean placement, pre-route.
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- `…kicad_pcb.bak-postAutoroute-20260703-202442` — routed, pre-fill (the 1072-seg import).
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- Fable's own `…bak-preroute-20260703-151135` and `…bak-leoclose-160912` retained.
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- DRC reports: `_route-continue-drc-{poststrip,postauto,postfill,clean}.txt`.
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## Related
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- [[watchdog-electrical-design-state]] (canonical electrical) ·
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[[watchdog-pcb-v3-kicad-guide]] (widths §6) · [[watchdog-production-schematic-delta]] · [[CLAUDE|Master Index]]
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