HBOX Watchdog v3 PROD — Routing Status (2026-07-03)

Board: kicad/hbox-watchdog-v3-PROD.kicad_pcb — 120×100 mm, 126 footprints. Continues the routing Fable started (and left broken by a mid-route spend-limit cutoff).

⭐ UPDATE 2026-07-03 — RESPUN TO 4-LAYER (the real fix)

The 2-layer board could not take wide power: FreeRouting left 51 unrouted even at a moderate 1.0/0.8 mm (and the intended 1.5+ mm was worse). That's the honest limit of 2 layers on a board this dense (3 switchers + 4G modem + RTK shield). Leo's call: respin 4-layer.

Stackup now 4-layer: F.Cu / In1.Cu (GND plane) / In2.Cu / B.Cu (JLC standard 1.6 mm; no explicit stackup block → JLC applies theirs). Converted by adding In1.Cu(id 4)+In2.Cu(id 6) as copper (KiCad 9 IDs verified empirically; hand-add_layer cascades junk — direct file edit used).
GND moved to the In1 inner plane (pour relayered B.Cu→In1.Cu, refilled). Exports as (plane GND (polygon In1.Cu …)) → FreeRouting bonds GND to the plane; routes on F/In2/B.
2-layer routing stripped for a clean 4-layer route.
Route artifact for Leo: kicad/hbox-watchdog-v3-PROD-4layer-wideclass.dsn (PWR_HI 1.5 mm, PWR_MID 1.0 mm, signals 0.2 mm, through-via Via[0-3], 4 routing layers). Run FreeRouting on the Mac → .ses → I import + refill In1 plane + DRC. Instructions: kicad/RUN-4layer-autoroute-README.md.
Order at JLC as 4-layer. Wide power now has room; solid GND is the reliability win we went for.
Backups: …bak-pre4layer-* (2-layer routed), …bak-pre4Lroute-* (4-layer pre-strip).

4-layer route imported (FreeRouting, 70 passes)

Leo ran FreeRouting on …-4layer-wideclass.dsn → 13 unrouted (vs 51 on 2-layer — the respin worked). SES imported: 862 tracks, 129 vias, In1 GND plane filled (8,550 mm²), no new shorts (the 5 shorting-item lines = placement baseline: J7↔MOD1 no-net under the shield ×4 layers + SYS5V↔SW_5V kiss). Wide power rails routed with real width — the goal.

Punch-list (finish in KiCad interactive router — fine-pitch, needs eyes; quick on 4-layer):

~7 IC-pad opens, all in the U3/U6 cluster (center): BAT_PLUS (U6.23), VIN_SW (Q7.5↔U6.7), IGATE (Q7.4↔U6.15), SW_5V (C3.1↔Q1.3), 3V3 (→U3.3), I2C_SDA (U3.1↔R31.2), I2C_SCL (U3.2). U3 = SHT40 (0.3–0.5 mm pads), U6 = LTC4040 QFN — the autorouter can't finesse these.
~10 GND pads not fully bonded to the In1 plane: THT — P10.2, P13.3, J1.19, J2.19, MOD1.6, J7.10 (fix: set In1 zone pad-connect to solid, or add a plane via); SMD — C7.2, C11.2, Rfreq.2, U3.4 (fix: short GND via to In1). Safe to do via MCP (GND-to-GND).
Minor: FreeRouting parked short BAT_PLUS/SW_5V segments on the In1 plane layer — reroute onto F/In2/B for a fully solid plane (cosmetic-ish for this slow board).

The 2-layer material below is retained for history; the board is now 4-layer.

What was done this session

Ripped up Fable's partial hand-route. It was interrupted mid-route with 19 net-to-net shorts (GND↔SYS5V, MAIN5V↔VIN_SW, 24V↔Q10_GATE…), 6 track crossings, 13 dangling vias — not salvageable. Stripped all routed copper (178 segments + 32 vias) back to clean placement; footprints, nets, and the B.Cu GND pour preserved. Backups kept (see below).
Net-classes / rules. Global clearance was 0 → fixed to 0.2 mm (would have let the router short). Project already carried PWR_HI/PWR_MID patterns (kept: PWR_HI = BAT_PLUS, SW_BAT, MAIN5V, VEH5V, SYS5V, VIN_SW; PWR_MID = SW_5V, 3V3_MODEM, 5V_FAN, 24V, 24V_IN, IGN_IN, SW_FAN, SW3_NODE, FAN_RET).
Autorouted with FreeRouting 1.9 (best-of-N, on the Mac's Java 23). Result imported: 1072 segments, 131 vias, 100 % of nets routed (0 unrouted at import), and — critically — no new shorts or clearance violations from the routing itself.
GND handled as a plane. The B.Cu GND pour exports as a real (plane GND), so FreeRouting bonded GND to the bottom plane instead of thin traces. Pour filled (8160 mm²).

Current DRC = 204 (down from Fable's 276)

Essentially the placement baseline + connectivity stragglers:

Bucket	Count	Nature
courtyards_overlap	67	by-design under-shield overlap (MOD1/J7/J8) — pre-existing
silk_overlap / silk_over_copper	59 / 50	cosmetic silkscreen — pre-existing
pth_inside_courtyard, lib_footprint, hole_to_hole, solder_mask	9/4/1/3	placement baseline
clearance	7	sub-mm placement pad kisses — pre-existing (in Fable's Jul-2 baseline)
shorting_items	3	placement, not routing: J7-Pin8↔MOD1-A5 (no-net, under shield) ×2; SYS5V↔SW_5V pad kiss — verify (real nets)
starved_thermal	1	one GND thermal relief with 1 spoke — trivial
unconnected_items	17	the routing punch-list ↓

Punch-list to fab-ready (the last 2 %)

A. Close 17 open connections (do in KiCad GUI — interactive route with copper visible; NOT blind by coordinate, which is how the 19 shorts happened last time):

U3 (SHT40) — 4 pins near-missed: pad1 SDA (65.3, 77.6), pad2 SCL (65.3, 78.4), pad3 3V3 (66.7, 78.4), pad4 GND (66.7, 77.6). Tiny 0.5×0.3 mm pads on 0.8 mm pitch; the I2C/3V3 tracks stop ~3–5 mm east near U4. Functionally critical (sensor won't work).
~13 GND-to-plane: edge THT grounds not reaching the plane — P5 pad2 (20.5, 6), H3 pad3 (31, 11), P13 pad3 (41, 6), MOD1 pad6 (72.7, 48), J1 pin19 (72.7, 16), J2 pin19 (72.7, 33.8) — plus a few GND track/via gaps mid-board. Fix by nudging the zone / short GND jumper to the plane body (visible in GUI).

B. Widen power nets to class widths. The autoroute ran at a uniform 0.2 mm (see tooling note) — power rails are currently thin. Widen to spec: PWR_HI ≥1.5 mm, PWR_MID/SW_5V ≥0.8–1.0 mm, signals 0.25 mm (per watchdog-pcb-v3-kicad-guide §6: power/5V ≥0.5, SW_5V ≥0.8). Easiest via GUI: select each power net → set width from net-class → push-and-shove reflows neighbors. This is the project's core reliability lever (voltage drop / heat) — required before fab.

C. Verify the SYS5V↔SW_5V placement kiss (bottom-right cutoff-switch area) — real nets.

Tooling notes (why power isn't already wide)

FreeRouting 1.9 jar needs Java 17+; the analysis sandbox only has Java 11 (no net to fetch a JDK) → can't run the jar there. The Mac has Java 23.
The KiCad-MCP export_dsn (swig backend) flattens all nets into one kicad_default class at 0.2 mm — it does not apply the PWR_HI/PWR_MID patterns. So the MCP autoroute (which re-exports internally) routes everything at 0.2 mm; the wide classes can't be driven through it.
MCP tool calls cap at 30 s, but FreeRouting finishes asynchronously on the Mac (~2–3 min) and the SES still imports — that's how this route landed despite a "timeout".
Path to wide-power autoroute (optional): inject PWR_HI/PWR_MID classes into the exported DSN and run java -jar freerouting-1.9.0.jar -de <fixed>.dsn -do out.ses on the Mac, then import_ses. Otherwise just widen in the GUI (recommended — current signal routing is good).

Backups (in `kicad/`)

…kicad_pcb.bak-preAutoroute-20260703-200734 — clean placement, pre-route.
…kicad_pcb.bak-postAutoroute-20260703-202442 — routed, pre-fill (the 1072-seg import).
Fable's own …bak-preroute-20260703-151135 and …bak-leoclose-160912 retained.
DRC reports: _route-continue-drc-{poststrip,postauto,postfill,clean}.txt.

watchdog-electrical-design-state (canonical electrical) · watchdog-pcb-v3-kicad-guide (widths §6) · watchdog-production-schematic-delta · CLAUDE

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