EinarBoard 3.0 — Design Brief ("the prompt")

How to use this doc. Self-contained instruction set for turning hbox-watchdog-v4 (EinarBoard 2.0, as sent to fab ~2026-08-01, git b505cb3) into EinarBoard 3.0 (kicad/hbox-watchdog-v5). Standing rules unchanged from the 1.1 brief: file-level KiCad edits only (KiCad MCP backend clobbered disk state 2026-07-24 — read-only MCP queries are fine); git checkpoint after every phase; verify every structural edit with an independent parse; bench gates unchanged.

0. Decisions locked 2026-08-12 (Leo)

Topic	Decision
MCU	On-board STM32F411RET6 (LQFP64) replaces the Blackpill module + J1/J2 sockets
Flash path	USB DFU on a board-mounted USB-C (BOOT0 + NRST buttons on-board, Blackpill parity) + SWD recovery pads
Base	`hbox-watchdog-v4` (EinarBoard 2.0: W5500 Ethernet, SC16IS752 serial, PCF8574 expander — all kept)
Modem / GNSS	Stay modular — XBee socket + simpleRTK2B Pro shield (stock already purchased)
Fixation	Shield bolted through its UNO-pattern holes into matching EinarBoard holes (M2.5); 2× M2.5 holes near the XBee for a heatsink that also clamps the modem
Fan	2-pin fan only — 4-pin header + tach conditioning removed, PB10 freed
Naming	Product EinarBoard 3.0 · KiCad project `hbox-watchdog-v5`

1. Why the F411RET6 (and not something else)

Same silicon family as the Blackpill's F411CEU6 → firmware v2.3/v3.x runs unchanged. Only the build target moves: Arduino board = Generic F411RE (or a copied Blackpill variant) with HSE_VALUE = 25 MHz — a build-config change, not a port.

	F411CEU6 (Blackpill chip)	F411RET6 (chosen)	G431CBT6 (rejected for now)
Package	UFQFPN48 (hot-air only)	LQFP64 — hand-solder/rework OK	LQFP48
JLC price/stock (2026-08-12)	$3.31 · 1,333 (C2054095)	$2.47 · 5,342 (C94355)	$2.96 · 13,744 (C529355)
Extra pins	—	PC0–PC12, PD2 (+ USART6 on PC6/PC7 = real 3rd UART; more ADC)	FDCAN (future CAN), crystal-less USB
Firmware	zero change	build-target change only	full port — wrong timing mid-fleet

The 1.1 brief's "F411 has no third USART" was a 48-pin-package limitation (USART6 lives on PA11/PA12 there = USB). On LQFP64 it's on PC6/PC7 — reserve them. If vehicle CAN ever becomes a requirement: MCP2518FD on SPI, or a G4 port as its own project. Source genuine ST via LCSC/JLC only — the ROM bootloader behavior is the product feature.

2. ⚠ THE BOOT TRAP — read before touching pins

DFU entry on the F411 requires, at reset: BOOT0 = 1 AND BOOT1 (PB2) = 0 (BOOT0=1 + PB2=1 boots SRAM = dead end). v4 has ETH_INT (W5500 INTn) on PB2, per the 1.1 note "BOOT1: irrelevant with BOOT0=0; do not strap" — which was true only while the MCU was a removable module. W5500 INTn idles HIGH → with the MCU soldered down, DFU would be unreachable. Therefore in v5:

Move ETH_INT PB2 → PC0 (EXTI0 is free: PA0/PB0 don't use EXTI).
Strap PB2 → 10 k → GND. Nothing else on PB2, ever.
ROM bootloader also listens on USART1 (PA9/PA10) = the Modo-B pins. Flash with the RTK stack unpowered (current practice) so F9P TX2 traffic can't capture the bootloader; if field-reflash-with-stack-on is ever needed, add a series jumper on the PA10 tap then.

DFU bootloader clocking: the F411 has no HSI48 — the ROM bootloader derives the 48 MHz USB clock from the external HSE crystal (4–26 MHz, auto-detected). Our 25 MHz HSE is therefore mandatory, not optional (AN2606; same reason the Blackpill carries one).

3. NEW Block P — on-board MCU (Blackpill absorbed)

U14 STM32F411RET6 (LQFP64, JLC C94355). Support circuitry, Blackpill-parity where noted:

HSE: 25.000 MHz crystal (3225, CL 10–12 pF) + 2× load caps C = 2(CL − C_stray) (≈15 pF for CL=10 pF; finalize per chosen crystal). Short symmetric traces, GND guard.
LSE: 32.768 kHz (3215/2012, CL 12.5 pF, e.g. Q13FC-class) + caps per CL. Fit it (Blackpill parity; RTC available). Firmware note: F411 LSE wants low drive level.
VCAP1: 4.7 µF X5R ≥6.3 V at the pin (DS10314 — confirm value/pin in Phase A).
Decoupling: 100 nF at every VDD pin + 4.7 µF bulk; VDDA: ferrite bead (or 10 Ω) from 3V3 + 1 µF + 100 nF (BAT_SENSE/VEH5V/NTC ADC quality — free upgrade vs the module's direct tie). VBAT → 3V3 + 100 nF.
BOOT0: dedicated pin → 10 k pull-down + tact switch to 3V3 (+ optional 2-pin jig pad). PB2/BOOT1: 10 k pull-down (§2).
NRST: joins the existing NRST net (SW1 on-board + P10 external — already designed)
- 100 nF at the pin.
LEDs: LED_C13 active-LOW (3V3 → 1 k → LED → PC13, Blackpill polarity so v2.3+ blink code is unchanged) + PWR LED on 3V3.
USB-C (J11): 16-pin USB 2.0 receptacle (TYPE-C-31-M-12 class) on a case-reachable edge. CC1/CC2 → 5.1 k to GND (UFP). D+ → PA12, D− → PA11 via USBLC6-2SC6 ESD array. Shield → GND via RC (1 MΩ ∥ 4.7 nF) or direct — decide Phase A.
SWD: 4 pads/test-points (3V3, PA13 SWDIO, PA14 SWCLK, GND) — DNP header. With a soldered MCU this is the brick-recovery + factory path; the 1.1 brief already wanted it.
PA0 note: no KEY button (Blackpill's KEY is PA0 = our BAT_SENSE). Not a loss.

4. Power — who makes 3V3 now

The Blackpill's on-module LDO dies with the module, so:

U15 LDO 3V3: AMS1117-3.3 (SOT-223, JLC Basic C6186) — or equal ≥500 mA. Budget: MCU ~50 mA + SHT40 + TMP102 + PCF8574 + SC16IS752 + MAX3232 + SP3485 TX bursts ≈ 150–250 mA worst → 1 A part with margin, ~0.3 W dissipation OK in SOT-223.
Input OR: LDO_IN = MAIN5V (via D_or1 SS34) ∥ USB VBUS (via D_or2 SS34). Bench flashing on USB alone powers the 3V3 domain only (MCU, sensors, expander, serial bridge): W5500 (3V3_ETH from SYS5V) stays dark, K1 stays NC (corrections path untouched), no backfeed into the LTC4040/MAIN5V. This replaces the module's VBUS-to-5V tie with something that can't fight the backed-up rail.
Phase-A sweep: every net the module's 3V3 pin used to source (I²C pull-ups, sensor VDD, PCF8574, SC16IS752, IOREF row to MOD1, D5 clamp reference, NTC divider top…) moves to the new LDO output net — keep the net name 3V3. Verify with a netlist diff.
3V3_MODEM and 3V3_ETH bucks: unchanged.

5. Fan — 2-pin, done

Fan connector → 2-pin (5V_FAN, FAN_RET). Remove the 1×04 header, FAN_TACH / FAN_TACH_RAW conditioning (pull-up/divider). Driver chain (PA6 FAN_PWM → Q → low-side) and the U2 fan buck stay exactly as-is.
PB10 freed (tach DNP provision retired — fleet fans are 2-wire, decided 2026-06-24).
Firmware v3.0 already plans tach-less fan-fault inference (temp climbs while PWM high).

6. NEW Block Q — fixation (mechanical)

Shield bolts: 4× holes in EinarBoard at exactly MOD1's UNO-pattern hole coords (read the NPTH positions out of the Arduino_UNO_R3 footprint in the v5 PCB — do not re-derive from a drawing). Drill Ø2.75 mm (M2.5); bolts pass shield → standoffs → EinarBoard (→ optionally the mounting plate). Bench check before freezing drill: caliper the real simpleRTK2B Pro holes — UNO-pattern boards are usually Ø3.2 (M3); if so either keep M2.5 hardware (washers, slop is fine) or open ours to Ø3.2 and use M3. Keepout annulus top/bottom, NPTH, no copper — and respect the HV24/inner-layer clearance rule.
XBee heatsink: 2× M2.5 holes near J7/J8 so a small heatsink/bracket bolts down and indirectly clamps the modem module. Position in Phase B with the case; keep clear of the RF side of the socket and the 24 V copper.
Case/plate: bolt pass-through and heatsink height ride the ASA reprint — coordinate connector-edge plan (USB-C now needs an opening too) before routing (Phase B gate, same as 1.1).

7. Pin map delta (v4 → v5)

Pin	v4 (EinarBoard 2.0)	v5 (EinarBoard 3.0)
PB2	`ETH_INT` (W5500 INTn)	BOOT1 strap: 10 k → GND. Nothing else.
PC0 (new pin)	— (module had no PC0)	`ETH_INT`
PB10	tach DNP provision	free (fan is 2-pin)
PA13/PA14	not broken out (module USB only)	SWD pads (DNP header)
PC6/PC7 (new)	—	reserved: USART6 (future 3rd UART)
PC1–PC5, PC8–PC12, PD2 (new)	—	free — do not spend without updating this table
PA11/PA12	module USB	J11 USB-C D−/D+
everything else	per watchdog-electrical-design-state §2 + 1.1 blocks M/N/O	unchanged

8. Depopulation / cleanup (3.0)

REMOVE: J1/J2 2×20 sockets + Blackpill-L/R symbols and footprint (→ errata E-J1 retired by construction — no module, no mirroring, no "never power a seated module" hazard); 1×04 fan header + tach parts; stale Blackpill silkscreen (module outline, header labels). KEEP: SW1 + P10 reset, P11 (jumper plug), P12 NTC, J7/J8 XBee, MOD1 shield sockets, J7 USB modem-config path. SILKSCREEN: USB-C "DFU: hold BOOT0" hint, SWD pad labels, hole callouts (M2.5), fan "2-pin 5V".

9. Risks / open items

PB2 strap is load-bearing (§2) — make it a Phase-D ERC-notes item like the SC16IS address strap was in 1.1.
LQFP64 symbol/footprint: use KiCad lib MCU_ST_STM32F4:STM32F411RETx + Package_QFP:LQFP-64_10x10mm_P0.5mm; save copies into the project libs (same policy as the RevNum_EJ1 footprint).
Blackpill variant nuances: confirm Generic F411RE Arduino variant boots USB CDC as today's build does (bench item F-1 on first article; SWD pads are the net if it doesn't).
Shield hole diameter verify (§6). · LSE drive/caps verify on first article.
DFU with stack powered = USART1 capture risk (§2) — procedure note, not hardware.
v4 boards at fab: 3.0 starts now as design work; nothing in 3.0 blocks v4 bring-up, and v4 bench findings (modem rail, LTC4040 timer behavior) feed Phase D review.

10. Execution phases (each ends: git commit + parse-verify + snapshot)

A. Schematic — copy v4 → hbox-watchdog-v5 (done 2026-08-12 with this brief); Block P + LDO OR (§3/§4); ETH_INT move + PB2 strap (§2); 3V3 net sweep (§4); fan 2-pin (§5); depop §8; ERC = 0.
B. Outline & placement — reclaim the Blackpill socket area; USB-C edge + case plan; Block-Q holes (shield coords from MOD1 footprint; XBee heatsink pair); Gate: Leo approves connector-edge + hole plan before routing.
C. Routing — MCU fanout (crystal + USB first), re-route displaced nets, zones refill; HV24 rules stand.
D. Verify — ERC/DRC clean; strap/boot checklist (BOOT0 pull-down, PB2 low, HSE present = DFU truth table); netlist diff v4→v5 reviewed; SVG/PDF review pack for Leo.
E. Outputs — gerbers/BOM/CPL, LCSC pass (C94355 + new passives/USB-C/LDO), delta-doc §-update, PINOUT.md rewrite (RET6 + freed pins), errata page (E-J1 retired), firmware ticket: build target Generic F411RE + HSE flag + PC0 EXTI for ETH_INT.

Fab gate unchanged: v5 doesn't go out before a v4-lineage bench validates the power path, and first-article v5 must prove USB DFU enumeration + a full flash cycle before any fleet quantity.

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