E1 clearance 0.1433 < 0.15 (/LED_A via vs /I2C_SCL via, 4 raw reports)
Relocated the /LED_A via 202c8cb4 from (147.15,85.85) to (147.25,86.22),
dead centre of the U13.1/U13.2 gap. uuid preserved; both attached segment
endpoints carried (In1.Cu 375e8fa7, B.Cu dee4fa4e). Worst gap now +0.2405.
E2 unconnected_items x2 + starved_thermal x1 -- ONE root cause.
The F.Cu GND pour pocket around U11 pad 29 was an island: it touched the
pad with a single thermal spoke but was fenced in by the LQFP-48 lead ring
and the escape routing, so it reached nothing else. Gave pad 29 a real
copper escape west to a new GND via that punches through to the In2 GND
plane, and set the pad to solid zone connection so the 2-spoke thermal
rule stops applying to a pad the pour can only reach from one side.
seg F.Cu w0.3 GND (99.4525,55.26)->(98.65,55.26) margin +0.2000
seg F.Cu w0.3 GND (98.65,55.26)->(97.55,54.45) margin +0.2000
via 0.6/0.3 F.Cu-B.Cu GND @(97.55,54.45) copper +0.2718
U11 pad 29 -> (zone_connect 2)
+0.2000 is the structural ceiling for a 0.5mm-pitch lead escape with a
0.3 track, and matches the neighbouring /3V3_ETH and /ETH_XI escapes.
E3 via_dangling /3V3_ETH via 3b0bb378 @(87.18,55.23) connected on F.Cu only.
Deleted. Touch test: 4 touching F.Cu segments, zero on In1/In2/B.Cu. The
F.Cu run at x=87.18 is collinear and continuous without it.
Verified: static DRC 0 hard violations (49 pre-existing marginals inside
KiCad's 0.0005 epsilon, unchanged). Per-net islands unchanged at 1 for
/LED_A /3V3_ETH /I2C_SCL /ETH_XI /ETH_RSET. New via lands inside
GND_PLANE_IN2 + GND_POUR_BCU, outside MAGJACK_NO_POUR. U11 is a plain
LQFP-48 with no exposed pad, so the under-body via is clear. Leo's 24V-class
copper (24V /24V_IN IGN_IN, 45 segments) byte-identical.
Backup: .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C12 (md5 7c2202cb)
New: md5 042efd5dd0cf99fdcfd27974b7bcb3c1 3502425 bytes
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Leopoldo Rodríguez
9512aa48cb
