Drogheda/03-Architecture-Hardware
Leopoldo Rodríguez b505cb35c2 v4 production package for JLCPCB: gerbers, BOM, CPL + audit
Fabrication Toolkit export of hbox-watchdog-v4 (EinarBoard 2.0), verified
before ordering. Board is 155.00 x 100.00 mm, 4 layers, 1.6 mm.

New in production/:
  HBOX_v4_PROD.zip             15 gerber + drill files
  HBOX_v4_PROD_bom.csv         102 lines, 25 with an LCSC number
  HBOX_v4_PROD_positions.csv   187 rows
  HBOX_v4_PROD_designators.csv toolkit by-product, not a JLC input

hbox-watchdog-v4.kicad_pcb is modified only because the toolkit's AUTO FILL
refilled zones and re-saved on export. Diffed before/after: 0 footprints
moved, 0 rotated, 0 changed side; tracks 1989 -> 1989, vias 351 -> 351,
zones 5 -> 5, filled polygons 41 -> 41. Zone fill data only.

Verification (details in the order walkthrough):
  - Row counts matched a prediction registered before the export existed:
    CPL 187, BOM 102, 35 machine-placed. No duplicate designators, no
    collisions from the toolkit's uppercasing of refdes, nothing truncated.
  - All 30 pre-registered rotation predictions matched exactly, 0 mismatches.
    The five previously-unproven packages resolved as J10 +0 deg and
    U10/U11/U13/U15 +270 deg.
  - Every non-zero rotation correction is externally backed: six packages
    (SOT-23, SOIC-8, SOIC-8-1EP, QFN-24-1EP, CP_Elec_6.3x7.7, Arduino_UNO_R3)
    are byte-identical to the v3 CPL that JLC built; the other four (LQFP-48,
    SOIC-16, SOIC-16W, TSSOP-28) match KiBot's published JLCPCB rotation
    table. KiBot's generic ^QFN- rule says 270 where the toolkit applied +90
    to U6 - v3 hardware settles it in the toolkit's favour.
  - Positions: 22 rows carry an AUTO TRANSLATE offset. 19 of 22 identical to
    the v3 export, 20 of 22 equal the pad bounding-box centroid to 0.02 mm.
    J10 is the only machine-placed part with a translation and it matches the
    centroid exactly.
  - Gerbers: 4 copper layers populated, both mask, both silk, F.Paste 40
    apertures. B_Paste empty is correct (the one bottom-side part has no
    paste). 523 PTH holes 0.30-1.63 mm, 6 NPTH at 3.20/3.25 mm.

Open before ordering: J10 (C12074 HR911105A) is the only through-hole part
carrying an LCSC number, so JLC's standard SMT line will not place it.
Also gitignore **/_to_delete/ (scratch folder for manual deletion).

Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
2026-08-01 06:57:17 +00:00
..
CAD-Files auto-sync 2026-07-13 18:00 2026-07-13 18:00:15 -06:00
circuitikz-wiring auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
EinarBoard-Manual sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
Guia-Conexion-Protoboard auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
kicad v4 production package for JLCPCB: gerbers, BOM, CPL + audit 2026-08-01 06:57:17 +00:00
Manual-Instalacion-Operacion Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
4G-USB-Reset-LED-addition.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
0007-1000_Assembly_Guide.pdf auto-sync 2026-07-11 18:00 2026-07-11 18:00:15 -06:00
2026-07-06_Drogheda_EinarBoard-1.0-PreFab-Audit_v1.0.md sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
2026-07-08_Drogheda_4G-Modem-Alternatives_v1.0.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
2026-07-24_Drogheda_EinarBoard-1.1_Design-Brief_v1.0.md EinarBoard 1.1 design brief: locked decisions (RS-485+RS-232 via SC16IS752, on-board W5500 Ethernet, RGB status LED, board growth) + execution phases 2026-07-29 01:58:39 +00:00
Assembly-BOM-Split.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
BOM-master.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
bom.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
cabinet-electrical-bom.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda_Conexiones-por-Bloque_Proto_v1.xlsx auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.png 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Diagrama-Cableado-Proto_ES.svg 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_EinarBoard-1.0_Tabla-Conexiones-Externas_v1.0.pdf auto-sync 2026-07-23 18:00 2026-07-23 18:00:14 -06:00
Drogheda_Guia-Cableado-Proto-Watchdog-v3_ES.pdf 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v2.2.pdf auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.0.pdf auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
Drogheda_Guia-Conexion-Protoboard_ES_v3.1.pdf auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
Drogheda-BOM-Maestro.xlsx Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
Drogheda-Manual-Instalacion-Operacion.pdf Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
EinarBoard-1.0-BOM-JLC-PCBA-v3-pinned-JLCPCB Assembly Order.xls sync: commit before registering as submodule 2026-07-08 14:58:40 -06:00
firmware-review-v2.3-EinarBoard.md Firmware review: v2.3 as EinarBoard 1.0 production candidate (2026-07-24) 2026-07-24 01:27:20 +00:00
firmware-review.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
hardware-respec-and-pcb-brief.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00
harness-connector-pinout.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
JLCPCB-Order-Guide.md auto-sync 2026-07-06 18:00 2026-07-06 18:00:09 -06:00
LCSC-search-list.md auto-sync 2026-07-07 18:00 2026-07-07 18:00:12 -06:00
Socket-Pinout-Silkscreen.md auto-sync 2026-07-05 18:00 2026-07-05 18:00:08 -06:00
watchdog-connections-rationale.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-connections.xlsx 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-electrical-design-state.md auto-sync 2026-07-09 18:00 2026-07-09 18:00:14 -06:00
watchdog-health-telemetry.md add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-LISTA-DE-COMPRAS-ES.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-pcb-v3-blockdiagram.svg auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-bom.xlsx add objectivity rule across all projects 2026-06-24 00:44:04 -06:00
watchdog-pcb-v3-design.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-pcb-v3-kicad-guide.md auto-sync 2026-06-22 18:00 2026-06-22 18:00:16 -06:00
watchdog-pcb-v3-routing-status.md auto-sync 2026-07-04 18:00 2026-07-04 18:00:09 -06:00
watchdog-production-schematic-delta.md 2026-07-02: PROD schematic complete (ERC 0) + carrier-board PCB + doc sweep to the Jul-2 ledger 2026-07-02 22:18:56 -06:00
watchdog-proto-bench-bringup-v3.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-protoboard-BOM-3boards.xlsx auto-sync 2026-07-20 18:00 2026-07-20 18:00:14 -06:00
watchdog-protoboard-bringup.md auto-sync 2026-07-03 18:00 2026-07-03 18:00:09 -06:00
watchdog-schematic.md Initial commit (Hub backfill) 2026-06-21 23:39:49 -06:00