Static-DRC battery (true pad geometry: circle/oval/roundrect/rect, NPTH as
hole-only) over 693 pads / 351 vias / 1982 segments -> 0 violations at the
project rule of 0.15mm min clearance, 0.25mm hole-to-hole.
Fixed:
[1] hole-to-hole -0.300 duplicate GND stitching via coincident at
(94.79,60.30) -- JLCPCB would have drilled the same hole twice. Removed.
[2] U11.13 (NC) +0.100 GND pad14 stub zigzag -> one straight lane x93.01
[3] U13.3 (GND) +0.130 I2C_SCL y=87.6 excursion -> single lane y=87.5277;
the GND stitcher the zigzag was dodging moved 0.138 north onto U13.2
pad copper (same uuid/net, still bonded to its track)
[4] ETH_LINKLED +0.130 3V3_ETH under-body via/rung -> y=57.455, the exact
centre of the only legal B.Cu window (RSET@56.89 / LINKLED@58.07);
165000nm both ways
[5] U11.17 +0.140 GND pad16 lane x94.14/94.15 -> single lane x94.10
[6][7] U11.46/47 +0.150 ETH_PMODE north lane y=49.31 -> 49.24
[8] stranded 1.5x1.5mm rule area (tracks/vias/pour not_allowed) nested in
U3's footprint but stranded ~22mm east of it with zero copper within
3mm -- a phantom no-route trap. Removed.
[9] stranded /3V3_ETH web on In2.Cu (the GND inner plane): orphaned remains
of the pad17 via removed in C10e, connected to nothing, punching a
clearance void in the GND plane. Removed.
Verified: paren balance 0; 188/188 footprints intact (only U3 shrinks, by the
nested rule area); top-level block census unchanged but segment 1992->1982 and
via 352->351; every touched net resolves to exactly ONE copper island
(/3V3_ETH went 2 -> 1); 24V-class hand-routed copper byte-identical
(24V 23 segs, /24V_IN 12 segs, IGN_IN 10 segs).
Pre-C11 board preserved at .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C11
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Leopoldo Rodríguez
f2232e9e4e