hbox-docs/docs/procedimientos/einarboard-1.0-bringup.md

title	tags	project	author	date	status
EinarBoard 1.0 (rev 1.1) — Bring-Up Runbook & Anticipated-Trouble Register	project-drogheda hardware einarboard bringup testing runbook	Project Drogheda	Helgen CTO	2026-07-08	ACTIVE — execute in order when boards arrive

EinarBoard 1.0 — Bring-Up Runbook

Order (FINAL — replacement of 2026-07-08): original PCBA SMT026070860564 cancelled (2 BOM lines lost at matching); replacement placed 2026-07-08, live-verified complete: 53 lines, 116/118 designators assembled incl. D2/DBK2/DBK1 and all six LEDs. Rotations confirmed by Leo in the placement viewer. Deltas vs the original parts map: LEDs = C2295 KT-0805R (RED — all indicators red by choice) · RS1 = C2988654 (HoLLR1206-1W-8mR-1%, spec-compliant alternate) · 100nF = C1591 · 22µF ×4 = C76637 · R51 = C22972 · 22k = C31850. J1/J2 NOT assembled (the only unselected parts) → bench jig-solder; buy two 1×20 2.54 female sockets locally (the C50984 reel is locked in JLC inventory for future PCBA). Setpoints re-derived from ordered values 2026-07-08: fan 4.99 V · modem 3.33 V · I_chg 2.42 A · input limit 3.12 A · PFI 4.61 V · backup 4.79 V — all on target.

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A. NOW — before production starts (the $479 gate)

• DFM Analysis check (4–6 h after ordering, Order History → DFM Analysis). Verify the polarity dozen against the answer sheet: U6 pin-1 TOP-LEFT · U2/U7 pin-1 BOTTOM-RIGHT · Q7 pin-1 TOP-LEFT · bands: D2/Dbk2/D5/D10 LEFT, Dbk1 TOP, D6 RIGHT · electrolytics "+": C3 BOTTOM, C10/C43 LEFT · LED cathodes LEFT (D1, D4G1, DB1–4). The preview already caught U6 and U2 turned 180° once — assume nothing.
• Confirm Production File is set to Yes with 48 h auto-confirm — an unwatched weekend approves itself. Approve only after the DFM check passes.
• Answer every JLC review email same day (schedule protection).

B. Reception (day of delivery)

• Visual vs the ordered renders: DNPs bare (P3/P13/H3, MOD1 field), all sockets present, P1 wire-entry toward the edge, J9 opening at the edge.
• Polarity dozen again, on physical boards, one board, 5 minutes with a loupe.
• Measure J1↔J2 socket spacing on one board (decision record says 15.00 mm) and test-insert a Blackpill — expect light preload if the module measures wider; note insertion force.

C. Board #1 electrical bring-up — NO modules socketed, current-limited bench supply

1. Resistance sanity (unpowered): 24V_IN→GND, MAIN5V→GND, 3V3_MODEM→GND — no shorts (>1 kΩ).
2. 24 V path: bench supply 24 V, limit 200 mA → P1 pins 1/2. Check: 24V rail after Q10 ≈ 24 V (reverse-protection FET conducting), 5V_FAN = 5.0 V (U2 running), fan header P6 pin 1.
3. Vehicle 5 V path: 5 V, limit 500 mA → P2. Check: MAIN5V ≈ 5 V (LTC4040 input FET passing), SYS5V after P11 jumpered/switched ON, Blackpill socket pins J1-20/J2-18 = 5 V.
4. Load switch default-OFF (invariant #1): with no MCU, SW_5V must be 0 V. Then short J1-7 (PWR_CTRL) to 3V3 momentarily → SW_5V = 5 V, 3V3_MODEM = 3.33 V (U7 up).
5. Ignition sense: 12 V and 24 V through P1-3 → IGN_SENSE (J1-11) clamps ≈ 3.5–3.6 V; 0 V → <0.3 V.
6. ⚠ CHARGER NTC TRAP (this WILL look like a dead charger): with no battery-harness NTC on P4-3, the LTC4040's NTC pin is pulled to VIN by R55 → reads "battery too cold" → charging silently paused. For bench charge tests, connect 10 kΩ from P4-3 to P4-2 (GND) to emulate 25 °C. Do not debug the charger without it.
7. Charger (with NTC emulation + real 1S4P pack or bench cell): connect pack to P4 → CHRG (J2-11) low while charging; charge current ramps ≤ 2.42 A; input current never exceeds ~3.1 A (watch the bench meter — this validates RS1/CLPROG behavior).
8. Backup event (THE LTC4040 validation — this block never saw a proto): system running on P2 5 V with pack connected → pull P2 → VSYS holds ≈ 4.79 V from boost, board keeps running. Measure: no back-feed voltage appearing on the disconnected P2 pins (validates Q7 orientation fix). Restore P2 → seamless return + recharge. Do this before any fleet commitment.
9. K1 fail-safe: unpowered board: continuity K1 pin 1 ↔ pins 5/6 (NC closed = corrections path exists with dead MCU). Powered + PB5 high: path opens to NO (pin 10).

D. Module integration (board #1 only, then replicate)

• MOD1 socket strips: solder using the simpleRTK2B Pro as the jig (strips on module → insert → solder → remove). Same jig trick for any stiff J1/J2 fit.
• Blackpill in (USB end toward board-left / VB-B12 corner at pads-1 — sockets don't key!). Flash bench firmware via module USB.
• Firmware flag: PROD CHRG_EN (PA8) is HIGH = charge OFF — the proto TP4056 logic was INVERTED (CHRG_RUN HIGH = ON). Port the flag before flashing, or units will disable charging when they mean to enable it.
• Pro into MOD1 (antenna top-left, USBs bottom, per the validated orientation). Old-rev Pros: XBee switch → UART1. All revs: Pro's own XBee socket stays EMPTY; never plug the Pro's "USB XBee" port in service (its FTDI sits on the RTCM3 downlink on new revs).
• F9P config: write to FLASH, not RAM (Jun-20 finding — RAM-only config dies at power cycle). Verify with a power cycle before shipping any unit.
• 4G NTRIP Master into J7/J8 (VCC row = J7). Telcel micro-SIM installed first. Board USB-C (J9) enables the modem's USB only when a host provides VBUS — bench console via J9 is safe; it does not fight the uplink.
• End-to-end: open sky, corrections from caster → GGA quality 4 (RTK fixed) — the fleet's first-ever verified fix ≥4 per the Jun-20 gap.

E. Known-accepted risks (decision register — watch, don't re-litigate)

Risk	Decision/owner	Watch for
J1/J2 rows at 15.00 mm vs 15.24 reading of module	Leo, vernier-verified, 2026-07-07	Insertion force; pin preload; use jig-solder trick if stiff
LTC4040 block fab'd without proto validation	Gate waived consciously (boards cheap)	Step C.8 is the validation — run it FIRST
C22 = 35 V part on 24 V node (spec said 50 V)	Accepted at order	Nothing expected; note for rev 1.2 BOM
C778721/C90142 ceramic bias derating	Within design margins	—
D4G1 modem LED driven from 1.8 V pin	Known-dim (audit L4)	Don't debug as a fault
Backup boost budget 1.93 A of 2.5 A at modem TX burst	Margin accepted; 104 µF VSYS bank	Brownout during TX only if budget exceeded — scope VSYS during TX test

F. Fleet replication (after board #1 passes everything)

Per-unit checklist: NTC harness populated (removes the C.6 emulation) · module orientations · switch-to-UART1 on old Pros · F9P FLASH config verified by power cycle · jig-soldered strips · GGA≥4 open-sky check · then HBOX integration per the enclosure docs (fit verified 2026-07-07).