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title tags project author date version status audience
EinarBoard v6 — Revisión final independiente (pasada 3, inglés)
project-drogheda
hardware
hbox
v6
esquematico
final-check
Project Drogheda Helgen Technologies 2026-09-28 1.0 FINAL — pass 3 of 3 (independent check) Michelle (layout), Leo, ingenieros

EinarBoard v6: final independent check of the ports pass, and closure of N1/N2 (v1.0)

!!! warning "EinarBoard v6 (hbox-watchdog-v6): en diseño, no se pide" Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. No es la V5.6 que se manda a fabricar esta semana (hbox-watchdog-v5, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.

!!! info "Pass 3 of 3 — final independent check" Spanish summary, final state per block and the combined layout delta: EinarBoard v6 — Cambios de esquemático: resumen de las 3 pasadas. Checks pass 2, closes N1/N2 from the verification of pass 1 (Spanish) and fixes the inductor land. Final schematic sha256 2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933.

Date: 2026-09-28 · Board: kicad/hbox-watchdog-v6.* (HBOX RTK, Helgen Technologies) · Input: sch f73f41a8…27ee (ports-pass output, verified on the Mac and in the staged copy) · Baseline for the ports diff: apply/netlists/05-final.xml · Author: Claude (final checker, independent of the apply and ports passes) · Rules followed: in-place edit with a backup first, span-scoped splices with a UUID multiset guard, expected changes written before editing, semantic netlist proof, .kicad_pcb not touched, no git, a unique staged path per commit plus sha256 on the Mac afterwards.

Resumen (ES)

Pase de puertos: 26 PASS, 1 FAIL. Revisé el pase de puertos por mi cuenta: diff propio desde 05-final.xml, conectividad derivada directamente del .kicad_sch (idéntica al netlist de kicad-cli: 353 redes, 0 diferencias) y hojas de datos de los fabricantes. Todos los cambios del esquemático son intencionales y correctos. Confirmé:

  • THVD1410 con el mismo pinout que el SP3485, 3–5,5 V y fail-safe abierto/corto/inactivo.
  • U32 74LVC1G04 en SOT-23-5 (1 NC, 2 A, 3 GND, 4 Y, 5 VCC). Según NXP, RTS̅ del SC16IS752 queda en ALTO tras el reset, así que el transceptor está en recepción durante el reset, en DFU y sin firmware. EFCR = 0x10 coincide con la tabla 30 de NXP.
  • SM712 bien orientado (pines 1 y 2 a A/B, pin 3 a GND).
  • TRS3232E con el mismo pinout y capacitores de 0,1 µF a 3,3 V.
  • R147 1 k y los CTS̅ a GND, correctos según NXP.
  • LED ACT de J10 (11/12) y J10.8 a GND: confirmados con el plano de Hanrun (amarillo con ánodo en 12 y cátodo en 11; P8 = «CHS GND», con la nota «Connect CHS GND to PCB Ground»). El pase de puertos no había podido leer ese plano. Los LED del W5500 son activos en bajo.
  • B-13: un solo excitador en /DIN_4G (PC6 → R148), sin contienda.
  • TP1–TP12 y JP1–JP6 fuera del BOM y del CPL.
  • Los 8 números LCSC existen, con stock y encapsulado correcto.

El FAIL es la huella H-03 IND-SMD_MWSA0804S. El pase de puertos intercambió las cotas J y H de Sunlord. La figura 4-1 de la especificación MWSA50230000 define I = largo del pad (2,75), J = separación entre pads (4,0) y H = alto del pad (5,5), y los electrodos están sobre la cota B = 8,8 mm. La huella tenía pads de 2,75 × 4,0 a ±4,125 mm (separación 5,5) y el cuerpo dibujado girado. Lo corregí: pads de 2,75 × 5,5 a ±3,375 mm (separación 4,0, extensión 9,5), cuerpo de 8,8 × 8,2 y courtyard de 10,0 × 9,0. El netlist no cambia (el nombre de la huella es el mismo). Esto sustituye las cifras de L-53.

N2 cerrado: se añadió C176 de 100 nF 0603 (C14663) entre /3V3_GNSS y GND, junto a U28 en la hoja, con la nota «≤ 2 mm from U28 pin 1». Lo esperado coincide exactamente con lo obtenido.

N1 cerrado sin cambio: la hoja de datos de SCTF (serie 3X, SMD3225-4P) da 1 Xtal, 2 GND, 3 Xtal, 4 GND, con la misma numeración de vista superior que la huella de KiCad. El mapeo Crystal_GND24 es correcto. Además, gm_crit = 0,50 mA/V (el F411 admite 1 mA/V) y la CL efectiva queda entre 9 y 11 pF para un cristal de 10 pF.

ERC: 0 errores, 134 warnings (igual que antes). Superposiciones 30 → 30 y cruces 9 → 9 (todos preexistentes). SHA-256 final del esquemático: 2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933. Ningún puerto queda bloqueado por el esquemático. Hay dos avisos que no bloquean: RXA flota durante la transmisión RS-485 (se resuelve en firmware), y la polaridad de USB_BOOT del A7670 es contradictoria entre documentos de SIMCom (hay procedimiento alterno en banco). Se añaden L-63…L-66 a la lista de Michelle.

0. Summary

Item Result
Ports-pass verification 26 PASS · 1 FAIL (the H-03 land pattern; fixed here, §3)
Diff 05-final → ports output (my own code) 8 added, 0 removed, 8 pin-net changes, 0 net-class changes; every change is on the intended list
Sch-derived connectivity vs kicad-cli netlist identical (353 nets, 0 partition differences, 0 name mismatches), at start and at the end
N2 C176 100 nF 0603 C14663, /3V3_GNSS–GND, beside U28; expected == actual
N1 No change: SCTF datasheet confirms pads 1/3 = crystal, 2/4 = GND
Fixes F2: Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod land corrected to the Sunlord drawing (no netlist effect)
ERC (kicad-cli via KiCad MCP) 0 errors, 134 warnings, before and after
Overlaps / wire crossings 30 → 30 / 9 → 9 (all pre-existing; C176 involved in none)
BOM 299 fitted real parts, all with LCSC numbers (298 + C176); TP1–TP12 and JP1–JP6 excluded; PF* virtual
Final sch sha256 2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933
Untouched .kicad_pcb 6ddec80d…36bf, .kicad_pro d577aa43…6ce, .kicad_dru 31ce0f4f…831

1. Ports-pass verification table

Method: I staged the Mac sch (sha256 f73f41a8…27ee, equal to the ports pass's claim and its container copy) and re-exported the netlist with the KiCad MCP (netlists/00-start.xml). I wrote my own semantic diff against apply/netlists/05-final.xml (work/fdiff.py, xml.etree only). I derived connectivity directly from the .kicad_sch with the apply-verifier's schconn.py/derive_compare.py after reading them. I used the manufacturers' datasheets through WebFetch and, for image-only PDFs, rendered them with pdf.js in the Mac's browser pane. The screenshots are in final/evidence/. The container and Mac shell proxies block ti.com, nxp.com and lcsc.com (403); I did not route around that.

# Item Intended Found Verdict Evidence / citation
1 Completeness of the change set only the ports/no-respin items Diff 05-final → current: +C175, D39, R145, R146, R147, R148, TP12, U32; 0 removed; pin changes J10.8/11/12, U10.2/16, U14.2/3, U15.12; field changes on D6, J10, K1, L2/L6/L8/L20, Q6, R40, R41, TP1–TP8, U14, U15; 0 class changes. Nothing else PASS work/diff_apply_to_start.json; equals ports/netlists/final.xml (0 differences)
2 U14 → THVD1410DR pinout = SP3485 (R, RE̅, DE, D, GND, A, B, VCC) TI D pkg: 1 R, 2 RE̅ (2 MΩ PU), 3 DE (2 MΩ PD), 4 D, 5 GND, 6 A, 7 B, 8 VCC. Netlist: 1 /SER_RXA, 2+3 /RS485_DE, 4 /SER_TXA, 5 GND, 6 /RS485_A, 7 /RS485_B, 8 /3V3 PASS TI THVD14x0 datasheet, pin functions table
3 U14 supply 3.3 V "3 V to 5.5 V"; U14.8 on /3V3; C84 100 nF on /3V3 (TI: 100 nF per supply) PASS TI datasheet
4 U14 fail-safe / ESD claims open, short, idle; IEC ESD "failsafe-high when … open-circuit … short-circuit … idle bus"; IEC 61000-4-2 ±18 kV contact, ±25 kV air; HBM ±30 kV; EFT ±4 kV; bus abs max ±18 V; R = Z when RE̅ = H PASS TI datasheet §7, function tables
5 U32 74LVC1G04 package pinout DBV: 1 NC, 2 A, 3 GND, 4 Y, 5 VCC TI DBV table matches; KiCad SOT-23-5 pads 1-2-3 on the left, 4-5 on the right (standard). Netlist: 2 /SER_DEA (U10.1 RTSA̅), 4 /RS485_DE (U14.2+3), 5 /3V3 (+C175), 3 GND, 1 NC PASS TI SN74LVC1G04 datasheet; SOT-23-5.kicad_mod
6 Direction polarity, receive in reset/DFU/no firmware DE = RE̅ = NOT(RTSA̅) RTSA̅ HIGH → DE = 0, RE̅ = 0 → receiver on, driver off. RTSA̅ LOW → DE = 1, RE̅ = 1 → transmit PASS logic plus items 7 and 8
7 SC16IS752 RTS̅ after reset HIGH NXP Table 5 "Output signals after reset": "RTS HIGH"; MCR and EFCR "all bits cleared"; MCR[1] = 0 → "force RTS output to inactive (HIGH)" PASS NXP SC16IS752/762 datasheet
8 Firmware note EFCR = 0x10 RTSCON = 1, RTSINVER = 0 EFCR bit 4 RTSCON "1: transmitter controls RTS pin"; bit 5 RTSINVER "0: RTS = 0 during transmission and RTS = 1 during reception"; §9.1 "asserts the RTS pin (logic 0) once the host writes data … de-asserts (logic 1) once the last bit … has been transmitted". 0x10 is right; bit 0 (9-bit mode) is not needed PASS NXP Table 30, §9.1/9.2
9 D39 SM712 orientation pins 1/2 to the lines, 3 to GND Semtech: "pins 1 and 2 have a working voltage of 12 volts … connected to the differential data line pairs … pin 3 … 7 volts … connected to ground". Netlist: 1 /RS485_A, 2 /RS485_B, 3 GND. KiCad SOT-23 pads 1/2 on one side, 3 opposite PASS Semtech SM712 datasheet Rev 6.0 (Mouser copy)
10 R145/R146 bias, DNP 3V3 → A, B → GND, 390 Ω, DNP R145 /3V3–/RS485_A, R146 /RS485_B–GND, both DNP; A > B idle = logic 1 (THVD1410: V_ID > V_TH+ → R = H). 3.3 × 60/(780 + 60) = 0.236 V with two 120 Ω terminations PASS netlist; TI receiver function table
11 U15 → TRS3232EIDR pinout = MAX3232 TI: 1 C1+, 2 V+, 3 C1−, 4 C2+, 5 C2−, 6 V−, 7 DOUT2, 8 RIN2, 9 ROUT2, 10 DIN2, 11 DIN1, 12 ROUT1, 13 RIN1, 14 DOUT1, 15 GND, 16 VCC; netlist matches pin for pin; narrow SOIC-16 land PASS TI TRS3232E datasheet
12 U15 charge-pump caps 0.1 µF at 3.3 V TI table at 3.3 V ± 0.3 V: C1 = 0.1 µF, C2–C4 = 0.1 µF, "C3 … VCC or GND". C85 C1±, C86 C2±, C87 V+ → GND, C88 V− → GND, C89 VCC, all 100 nF C14663. Unused DIN2 to GND ("connected to VCC or ground") PASS TI datasheet
13 R147 1 k on R1OUT (H4) R1OUT → R147 → /SER_RXB; H4.3 on the U10 side /RS232_R1OUT = {U15.12, R147.1}; /SER_RXB = {U10.24, H4.3, R147.2}. An external TTL driver sees ≤ 3.3 mA of contention; RC ≈ 10 ns PASS netlist
14 CTSA̅/CTSB̅ tied to GND GND, auto-CTS off NXP: CTS̅ LOW = ready; "only affects the transmit and receive operations when Auto-CTS function is enabled via EFR[7]". Tied LOW is the safe choice: it can never block TX, even if auto-CTS gets enabled PASS NXP Table 2
15 J10 ACT LED pin 11/12 swap yellow A = 12, K = 11 Hanrun HR911105A drawing, p.1 schematic: "Yellow LED" with pin 12 on the anode and pin 11 on the cathode; "Green LED" with pin 9 on the anode and pin 10 on the cathode. Netlist: 12 /ETH_ACT_A (R97 330 Ω → /3V3_ETH), 11 /ETH_ACTLED (U11.27); 9 /ETH_LNK_A (R96), 10 /ETH_LINKLED (U11.25) PASS evidence/hanrun_HR911105A_p1_schematic.jpg (rendered from lcsc.com/datasheet/C12074.pdf)
16 J10.8 → GND Bob-Smith return Hanrun: "CHS GND P8", through 1000 pF 2 kV to the 4 × 75 Ω node; note "Connect CHS GND to PCB Ground". P7 = NC. P4/P5 = TX/RX centre taps (J10.4 /3V3_ETH, J10.5 /ETH_RCT) PASS same page
17 W5500 LED drive polarity active-low, so the LEDs light W5500 v1.1.0: LINKLED (25) "Low: Link is established"; ACTLED (27) "Low: Carrier sense from the active PMD"; VOL 0.4 V at IOL 8 mA. LED current ≈ (3.3 − 2.0)/330 ≈ 4 mA (HR911105A LEDs: Vf 1.8–2.8 V, 20 mA rated) PASS WIZnet W5500 datasheet v1.1.0; Hanrun p.2
18 H-03 footprint IND-SMD_MWSA0804S land Sunlord recommended land Wrong. Sunlord MWSA-S spec (SPEC No. MWSA50230000) Fig. 4-1 (applies to MWSA0412S–MWSA1265S): I = pad length along the axis, J = gap between pads, H = pad height across; electrodes at the B ends (D = depth along B, E = height along A). Table 4-1 MWSA0804S: A 8.2±0.3, B 8.8±0.4, C 3.8±0.2, D 1.4±0.3, E 5.0±0.3, I 2.75, J 4.0, H 5.5. The ports pass read J as pad width and H as the gap (and took A as the electrode axis), which gave 2.75 × 4.0 pads with a 5.5 gap at ±4.125 mm. Correct: 2.75 × 5.5 pads with a 4.0 gap at ±3.375 mm FAIL → fixed (F2) evidence/sunlord_MWSA-S_fig4-1_land.jpg, …fig4-1_body.jpg; Table 4-1 row read from the PDF text layer
19 H-03 body vs courtyard body fits the courtyard The old courtyard (11.5 × 9.7) did enclose the body at maximum tolerance in either orientation, but the F.Fab outline was rotated (8.2 on the pad axis instead of 8.8). Fixed with item 18: body 8.8 × 8.2, courtyard 10.0 × 9.0 (max of pads 9.5 / body 9.2 on x, body 8.5 on y, plus 0.25) PASS (after F2) §3
20 B-13 topology PC6 USART6_TX → R148 → /DIN_4G → U23 (B → A) → modem RXD /USART6_TX = {U16.37, R148.1, K1.10 (DNP)}; /DIN_4G = {R148.2, R143.2 100 k PU, U23.7 1B, K1.5/6 (DNP), R108.1 (DNP, never-fit)}; U23.5 DIR = GND → "B data to A" (1B input, 1A output); /DIN_4G_M = {U23.2, U19.10 RXD, R108.2 (DNP)}; U23 VCC(A) = /1V8_MODEM, VCC(B) = /3V3 PASS netlist; evidence ic_pins_U19.csv (pin 10 RXD)
21 Drivers on /DIN_4G and neighbouring nets no two outputs on one net Before (05-final): /DIN_4G driven only through K1 COM, from either NC = F9P TXD2 (/USART1_RX) or NO = PC6, never both. After: /DIN_4G has one driver, PC6 via R148; /USART1_RX has one driver, F9P TXD2 (U18.27), with PA10 as input and Rdfu1 as PU; /DIN_4G_M has one driver, U23.1A; /BYP_CTRL (PB5) is now unloaded (R40 DNP); /KCOIL and /Q6_BASE are all DNP. Fitting K1 together with R148 would put F9P TXD2 against PC6 (both notes say "never") PASS §1.1 table
22 TP12 (1V8) 1V8 pad beside TP8 for forced download TP12 on /1V8_MODEM (U19.15 VDD_1V8/_EXTVDD). SIMCom "A7670 Series Hardware Design V1.00" (A7670C/E/SA): USB_BOOT pin 6 B-PD; "pull the USB_BOOT pin to 1.8V, then apply VBAT … to enter the download mode". "A7670 & SIM7070 & A7672X Compatible Design V1.02": A7670X pin 6 marked "●" = "cannot be pulled up before the module powered up"; "pull up the USB_BOOT pin to 1.8V for A7670". The v6 symbol names the pin USB_BOOT●. Conflict: "A7672X/A7670X Series Hardware Design V1.03" lists A7670SA and gives USB_BOOT B-PU with "pull the USB_BOOT pin to GND". TP12 matches two SIMCom documents; a GND fallback is recorded (A2, L-65) PASS (with note A2) SIMCom documents as cited
23 TP1–TP8 out of BOM/CPL in_bom no, in_pos_files no TP1–TP12 and JP1–JP6 all in_bom no, in_pos_files no, on_board yes; none appears in the kicad-cli BOM PASS sch flags; bom_final_ungrouped.csv
24 New/changed LCSC numbers exist, package, stock C2671345 THVD1410DR SOIC-8, 8 006 (Extended, pre-order category) · C7827 SN74LVC1G04DBVR SOT-23-5, 163 327 · C12067 SM712.TCT SOT-23, 49 238 · C308878 TRS3232EIDR SOIC-16 (narrow), 3 564 · C14663 100 nF 0603 X7R 50 V, Basic, 37.5 M · C23151 390 Ω 0603, Basic, 311 280 · C21190 1 kΩ 0603, Basic, 39.8 M · C21189 0 Ω 0603, Basic, 13.9 M. Inductors unchanged: C17700171 (470), C17700165 (646), C17700167 (1 675) PASS get_jlcpcb_part (all 11)
25 ERC 0 errors 0 errors / 134 warnings at start (same families as reported) PASS KiCad MCP run_erc
26 Sch ↔ netlist derived = exported 353 = 353 nets, 0 differences, 0 name mismatches (variant MR, −1, wire-interior on) PASS derive_compare.py
27 Overlaps / crossings not worsened 30 / 9. The two crossings on U10 (x = 551.18) and the four on U15 pre-date the ports pass (21 wires added, 0 removed, none of them among the crossings) PASS MCP checks; wire diff vs ports/state/00-pre.kicad_sch

1.1 Drivers per net, before and after (B-13)

Net Before (05-final, K1 fitted) After (current) Outputs fighting?
/DIN_4G K1 COM (5/6), R143 100 k PU, U23.7 input, R108 DNP R148 ← PC6 (single driver), R143 PU, U23.7 input; K1 and R108 DNP No
/USART6_TX U16.37 PC6, K1.10 (NO) U16.37 PC6, R148.1; K1.10 DNP No
/USART1_RX U18.27 F9P TXD2, U16.43 PA10 input, Rdfu1 PU, K1.1 (NC) U18.27, PA10, Rdfu1; K1.1 DNP No
/DIN_4G_M U23.2 (1A out), U19.10 RXD, R108 DNP unchanged No
/BYP_CTRL PB5 → R40 → Q6 → K1 coil PB5 only (R40 DNP): set it as output LOW or analog in firmware —

When the MCU is in reset or DFU, PC6 is Hi-Z and R143 holds /DIN_4G HIGH (UART idle). With the modem off, 74LVC2T45 Ioff isolates the A side.

1.2 Advisories (not failures; nothing to change in the schematic)

  • A1. RXA floats during RS-485 transmit. With RE̅ tied to DE, THVD1410 R = Z whenever DE = 1 (TI receiver table), and NXP documents no pull-up on RXA. TI's own typical application ties R straight to the UART RX, so this is not a datasheet violation and does not stop the port. The SP3485 behaved the same way. Firmware: after each frame, wait for LSR[6] (TEMT), reset the RX FIFO (FCR[1]), read LSR to clear any error flags raised during TX, and only then arm reception. An alternative is EFCR[1] RXDISABLE while transmitting. A 10 k pull-up on /SER_RXA would make this unnecessary, but it is an optional robustness item, not an error, so it was not added.
  • A2. USB_BOOT polarity conflict in SIMCom documents (item 22). The bench procedure is to short TP8–TP12 at modem power-on; if the download port does not enumerate on J9, short TP8 to GND instead. L-65 keeps a GND point within reach.
  • A3. Cosmetic: pre-existing text crowding at U14 value / R82 / JP5 and C85–C88 on U15 (already in the 30-overlap baseline). No electrical effect.
  • A4. The ports report quotes the SM712 at 400 W (8/20 µs, the LCSC description); the Semtech Rev 6.0 sheet lists a higher peak pulse power class. Either value suits a cabinet-internal RS-485 run.

2. N1 and N2

N2: TPS2552 input decoupling (U28)

TI TPS255x: "Input voltage; connect a 0.1 µF or greater ceramic capacitor from IN to GND as close to the IC as possible." U28 DBV pin 1 = IN = /3V3_GNSS. The existing C170 (100 nF on /3V3_GNSS) sits elsewhere on the sheet (U27/F9P area), so it does not meet "close to U28".

Done: C176 = 100 nF 0603, LCSC C14663 (Basic, 37.5 M in stock), pin 1 /3V3_GNSS, pin 2 GND. It sits at sheet (457.2, 182.88) rotated 90°, directly above U28, with the sheet note "N2: C176 = U28 IN decap, <=2 mm to U28.1" and a Note field that states the layout rule. C176 is the next reference after the highest used (C175); none of the gap numbers exists on the PCB either.

N1: Y3 pad assignment (SCTF SX3B25.000F1010F30, C2901684)

Confirmed from the manufacturer datasheet: SCTF "3X Series 3.2 × 2.5 mm SMD Crystal" (LCSC copy 2110101030_Shenzhen-SCTF-Elec-SX3B25-000F1010F30_C2901684.pdf, rendered with pdf.js). The pin table reads 1 Xtal, 2 GND, 3 Xtal, 4 GND. The top view numbers 1 bottom-left, 2 bottom-right, 3 top-right, 4 top-left, which matches KiCad Crystal_SMD_3225-4Pin_3.2x2.5mm (pad 1 at (−1.1, +0.85), 2 at (+1.1, +0.85), 3 at (+1.1, −0.85), 4 at (−1.1, −0.85)). The netlist has Y3.1 /HSE_IN, Y3.3 /HSE_OUT, Y3.2/Y3.4 GND. No change.

Cross-checks from the same sheet: CL 6–20 pF (part code "10" = 10 pF), C0 ≤ 3 pF, ESR ≤ 30 Ω (20–54 MHz), drive level typ 10 / max 100 µW. From ST AN2867: gm_crit = 4 · 30 Ω · (2π · 25 MHz)² · (3 + 10 pF)² = 0.50 mA/V, against the STM32F411 HSE Gm_crit_max of 1 mA/V (margin 2). C113/C114 = 12 pF give CL_eff = 6 pF + Cstray (3–5 pF) = 9–11 pF for the 10 pF part. evidence/sctf_3X_p1_specs.jpg, sctf_3X_p2_pinout.jpg.

3. Fixes, with proof

F1: N2 (schematic)

  • Expected, written before editing (out/F1-N2/expected_written_before_edit.json): +C176 {100nF, Capacitor_SMD:C_0603_1608Metric, Device:C, LCSC C14663, fitted, in BOM/CPL, 1:/3V3_GNSS, 2:GND}; /3V3_GNSS gains C176.1; GND gains C176.2; nothing else.
  • Edit: tools/gF1_n2.py uses the apply-pass editor (apply/tools/ops.py: splice-only, UUID multiset guard). The text diff is 152 lines added, 0 removed or changed: 1 symbol, 2 wires, 2 labels, 1 text. The C176 field angles were set to 90 to match the sheet's other rotated passives (L6, RS1), patching only the block the script generated.
  • Actual: netlist 00-start.xml → final.xml: added 1 (C176, exactly the expected attributes and pins), removed 0, field changes 0, pin changes 0, class changes 0, membership changes as expected. EXPECTED == ACTUAL. Sch-derived connectivity also shows only the GND and /3V3_GNSS groups changed.
  • Structural checks: orphan NC flags, NC on connected pins, dangling wire ends, dangling labels and unconnected pins without NC all stay at 0 → 0.

F2: H-03 land pattern (library file Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod)

  • Error, with evidence: item 18 (Sunlord MWSA50230000 Fig. 4-1 and Table 4-1).
  • New geometry: pads 1/2 SMD round-rect 2.75 × 5.5 mm at x = ∓3.375 mm (gap 4.0, outer extent 9.5); F.Fab body 8.8 (x) × 8.2 (y); F.CrtYd 10.0 × 9.0 mm; silk lines at y = ±4.21 (≥ 1.4 mm from the pads); Reference/Value at y = ∓5.5. All 11 UUIDs of the old file are kept; the name is unchanged, so L2/L6/L8/L20 keep the same footprint link and the netlist is unaffected.
  • Coverage at the tolerance extremes: the electrode spans x = 2.9…4.6 mm (B 8.4–9.2, D 1.1–1.7), inside the pad's 2.0…4.75 mm; E ≤ 5.3 mm fits inside H = 5.5 mm. The electrode is fully wetted, with a 0.35 mm toe and a 1.0 mm heel as Sunlord specifies. This land is also closer to the old SRU8028 land (outer ±4.9 mm) than the ports-pass version (±5.5 mm), so it disturbs placement less.
  • Old file backed up; sha256 dbf53557…a71f → 74528135d4f69617df8570da58700bac3920827a78ec9104c3440be2c5975638. The KiCad MCP cannot open project-local libraries; the file parses cleanly (sexpdata) in KiCad 9 writer format, and ERC (which checks footprint links) reports 0 errors.

Hashes and commits

Step File sha256 (Mac, checked after every commit) Staged path used
start hbox-watchdog-v6.kicad_sch f73f41a8…27ee — (backup _to_delete/v6-final-20260928/00-pre/)
F1 (first write) sch 889b3c32…1ef /mnt/user-data/outputs/v6final-F1-N2-20260928a/
F2 IND-SMD_MWSA0804S.kicad_mod 74528135…5638 /mnt/user-data/outputs/v6final-F2-H03-20260928b/
F1 (fields horizontal, final) sch 2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933 /mnt/user-data/outputs/v6final-F1b-N2-20260928c/
PDF 03-Architecture-Hardware/hbox-watchdog-v6-schematic.pdf ae88d524…746b (old 41241140…91b0 in 00-pre/) exported by the KiCad MCP

The only difference between the two F1 writes is C176's own UUID; C176 was never on the PCB.

4. ERC

State Errors Warnings Overlaps Crossings
Start (f73f41a8) 0 134 30 9
After F1 + F2 (final) 0 134 30 9

5. Final state

  • Schematic sha256: 2b394ef927a42823bde3f2a0408860d7c6d3784ab7d7ae3e66f46681f02f5933
  • Total vs the apply-pass final (05-final.xml): +9 parts (C175, C176, D39, R145, R146, R147, R148, TP12, U32), 0 removed, 8 pin-net changes (J10.8/11/12, U10.2/16, U14.2/3, U15.12), 0 net-class changes.
  • Final netlist: final/netlists/final.xml (sha256 7b65595f…607c; Mac copy _to_delete/v6-final-20260928/netlists/final-b.xml).

6. Additions to Michelle's layout list (continuing from L-62)

63. MWSA0804S land corrected (supersedes the figures in L-53). L2/L6/L8/L20 now use pads of 2.75 × 5.5 mm at ±3.375 mm (gap 4.0, outer extent 9.5), courtyard 10.0 × 9.0 mm, with the body's 8.8 mm side along the pad axis. The land is smaller than the ports-pass version (11.5 × 9.7) and close to the old SRU8028 land, so neighbour spacing is easier than L-53 said. Keep L-11/L-21/L-22/L-23 distances measured to the new pads. If the ports-pass version of this footprint was already pulled into the board, refresh only these four refs from the library (L-45).

64. C176 (N2): 0603 ≤ 2 mm from U28 pin 1 (IN), on the same layer as U28. Its GND pad goes to the GND plane through a via ≤ 1 mm away, and U28 pin 2 uses the same GND region. Feed /3V3_GNSS to U28.1 through the C176 pad (the cap sits between the supply trace and the pin).

65. TP8 / TP12 forced-download pads (A2): TP12 (1V8) at 2.54 mm from TP8 (L-55), plus a GND contact within 10 mm of TP8, such as J9's shell tab (SH = GND) or another GND pad. Silk: "BOOT: TP8–1V8 (alt: TP8–GND)".

66. J10 LED routing check: after Update PCB, confirm pad 12 = /ETH_ACT_A (to R97) and pad 11 = /ETH_ACTLED (to U11.27), per the Hanrun drawing (yellow A = 12, K = 11). Pad 8 = GND per the Hanrun note "Connect CHS GND to PCB Ground" (L-52).

7. Firmware notes added (FW 0.7.x board_v6.h)

  1. RS-485 RX hygiene (A1): flush the RX FIFO and clear LSR after each transmitted frame (LSR[6] TEMT → FCR[1]), or use EFCR[1] RXDISABLE during TX. Keep EFR[6] (auto-RTS) and EFR[7] (auto-CTS) = 0 while EFCR RTSCON = 1.
  2. PB5 (BYP_CTRL) is unconnected now (R40 DNP): configure it as output LOW or analog.
  3. Modem forced download: try TP8–TP12 (1.8 V) first; if J9 does not enumerate the download port, use TP8–GND (A2).

8. Anything that still blocks a port or the order

Nothing in the schematic. Remaining conditions:

  • Layout: L-49…L-66, especially L-63 (use the corrected MWSA land before routing the switchers) and L-64.
  • Library pass (optional): Drogheda-sym:TPS2552DBV is still embedded-only (from the apply pass).
  • Order logistics: pre-order THVD1410DR (C2671345, JLC pre-order category), U21 and J14; buy the P11/P12 mating plugs.
  • Bench, first board: both J10 LEDs light with link up; RS-485 idles in receive during MCU reset and in DFU; RS-485 loopback with EFCR = 0x10 (checking the A1 FIFO handling); RS-232 and H4 checks; J9 download mode (TP8–TP12, then TP8–GND if needed); L6/L8/L20 solder joints inspected on the new land.

9. Files

  • This report: /home/claude/v6audit/final/2026-09-28_Drogheda_EinarBoard-v6_Final-Check_v1.0.md
  • Final netlist: final/netlists/final.xml; start: netlists/00-start.xml; intermediate: netlists/01-N2.xml
  • Final schematic copy: final/hbox-watchdog-v6.kicad_sch.final; footprint: final/IND-SMD_MWSA0804S.kicad_mod.final; PDF: final/hbox-watchdog-v6-schematic.pdf; BOM: final/bom_final_ungrouped.csv
  • Proof: final/out/F1-N2/ (expected written before the edit, edit log, output), final/out/F2-H03/, final/work/diff_*.json, final/work/fdiff.py
  • Scripts: final/tools/gF1_n2.py
  • Datasheet evidence: final/evidence/ (Hanrun p.1/p.2, Sunlord Fig. 4-1 body and land, SCTF p.1/p.2, sheet crop of U28/C176)
  • Mac backups: kicad/_to_delete/v6-final-20260928/ (00-pre/ sch and old PDF, 01-N2/ post and post-b, 02-H03-land/ pre and post footprint, netlists/, BOM, new PDF)
  • Git (for Leo; nothing was run here): in the kicad submodule commit hbox-watchdog-v6.kicad_sch and Drogheda-v6.pretty/IND-SMD_MWSA0804S.kicad_mod, then bump the parent gitlink with git -c diff.ignoreSubmodules=none commit …. If KiCad is open on v6, close it without saving before Update PCB.

10. F3: LFP-HT backup-pack straps (mirror of V5.6)

Resumen (ES): v6 quedó con los mismos estrapes del cargador que V5.6 para el paquete LFP-HT 26650: JP2 puenteado 2-3 (F2 a GND) y R55 = 5.6 k (C23189). Flotación 3.50 V (antes 4.00 V Li-ion). Netlist: 0 cambios de pin o de red. ERC 0 errores (135 avisos). Esquemático d58a89ba…e7b.

Reason. On 28-Sep Leo chose a high-temperature LiFePO4 26650 pack for V5.6, and v6 uses the same pack family. v6 was still strapped Li-ion (JP2 F2 high, R55 10 k): an LFP pack would have floated at 4.00 V instead of about 3.50 V (overcharge hazard).

Ref V5.6 (reference) v6 before v6 after
JP2 (F2) Jumper:SolderJumper_3_Bridged23, fp Drogheda:SolderJumper-3_P1.3mm_Bridged23_RoundedPad1.0x1.5mm, value F2:LFP (2-3) Bridged12, F2:Li-ion = V5.6, Note "LFP-HT (F2 low), same as V5.6"
R55 (RNTB) 5.6k/1 % 0603, C23189, /VEH5V–/NTC 10k/1 %, C25804 5.6k/1 %, C23189
JP3 (F1), JP4 (F0) F1 = 0, F0 = 1 same unchanged
  • Netlist confirmation: U6.12 F2 = /F2_SEL = {JP2.2}; U6.13 F1 = {JP3.2}; U6.14 F0 = {JP4.2}; U6.17 NTC = {R55.2, P3.3, R137.1}; R55.1 on /VEH5V (the RBIAS of the ADI datasheet).
  • Float voltage (ADI LTC4040 datasheet, pin-function table): F2 = 0 selects LiFePO4; (F1, F0) = (0, 1) → 3.50 V.
  • Charge window with R55 = 5.6 k and a 10 k B3380 NTC: hot pause +60 °C, cold ≈ +8 °C on v6 (the F-51 tap R137/R138 shifts the cold trip about 2 °C).
  • Proof: expected changes written before the edit; netlist diff: 0 added, 0 removed, 0 pin-net, 0 membership and 0 class changes; only JP2 value/footprint/lib/Note and R55 value/LCSC/Note changed (plus JP2's footprint-filter text, which follows the symbol swap exactly as on V5.6).
  • ERC: 0 errors, 135 warnings (+1: the embedded Bridged23 symbol is not in the KiCad library, as on V5.6).
  • Hashes: sch 2b394ef9…2f5933 → d58a89ba5a5ac46419edf9d68672a8208d825a16387298d0167e21399cd41e7b; PDF 3e073181…4362; PCB 6ddec80d… untouched.
  • Layout L-67 (safety): after Update PCB confirm JP2 is the Bridged23 footprint with copper on pads 2-3 and no 1-2 bridge left; silk "F2: LFP".
  • Firmware / bench: measure /F2_SEL = 0 V, /F1_SEL = 0 V, /F0_SEL = MAIN5V on the first board before connecting a pack; rescale the PC5 NTC conversion (RBIAS 5.6 k, β 3380); raise the CHRG_EN hot cut in step with +60 °C; LFP-appropriate SoC thresholds or coulomb counting.