hbox-docs/docs/hardware/v6-prefab-audit.md

title	tags	project	author	date	version	status	audience
HBOX v6 — Pre-fabrication audit and work list	project-drogheda hardware hbox v6 pcb audit jlcpcb	Project Drogheda	Helgen Technologies	2026-09-25	1.0	ACTIVE — do NOT order until section 3 is closed	Michelle (layout), Leo

HBOX v6 — Pre-fabrication audit

Board: hbox-watchdog-v6 (repo HBox_PCB) · Planned order: 5 prototypes at JLCPCB (PCB + assembly) · Date: 25-Sep-2026 · Versión en español

!!! danger "Verdict: NOT ready to order yet" Everything that depended on the schematic, BOM and attributes is already fixed (section 2). What's left is layout work (section 3, Michelle) and three decisions/purchases (section 4, Leo). When Michelle pushes her work, Claude re-runs the full audit and gives the final GO.

Status today: DRC 0 errors, 0 unconnected, 0 dangling tracks · ERC 0 errors · BOM: every populated part has a verified LCSC number.

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1. Why "DRC 0" isn't enough

DRC only compares geometry against the file's own clearance rules. It cannot see:

• a switching regulator with its diode 18 mm away (it must be ≤ 4 mm),
• a 0.25 mm track carrying 2.5 A,
• a part with no LCSC number (JLC simply doesn't place it),
• a power chip with no vias under its thermal pad.

That's what this audit checked.

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2. Already fixed (nothing to do)

#	What	Detail
✅	SIM: the physical SIM holder is now the primary SIM	Telcel won't supply the MFF2. J14 (JAE nano-SIM, LCSC C2977286) + R131–R134 are fitted; U22 (MFF2) + R127–R130 are not fitted (DNP). The MFF2 footprint stays on the board as a future option.
✅	U19 (modem) and L22 set to SMD	They were marked "through-hole", so JLC would have left them off the SMT line. Also fixed in the library.
✅	64 parts with no LCSC number	All given verified numbers from the JLC database (Basic where possible). JP1–JP5 (solder jumpers) removed from the BOM.
✅	Input fuse F2	Now a fuse in a holder: Littelfuse 0154002.DR (C206910), 9.7 × 5 mm SMD block with a 2 A / 125 V NANO2 fuse. In the field the fuse pulls out and is replaced without soldering. (The PCB footprint still has to be swapped → task M2.)
✅	Mounting holes	All 4 on an exact 130.0 × 90.0 mm rectangle, 5 mm from each edge; unique names MH5–MH8.
✅	Cleanup	6 dangling track pieces deleted; "respaldo" copies out of git; power-width rules added to DRC.

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3. What's left — Michelle's work list

!!! warning "Before you start — three rules" 1. git pull first. Claude changed the .kicad_pcb today (attributes, LCSC, holes, fuse). If you work on an old copy and save it, all of that is lost. 2. Do NOT use "Update PCB from Schematic" until Leo decides J10/P11/P12 (section 4): it would set them back to fitted. 3. If KiCad says the file changed on disk, choose Reload. Never save an old copy over it.

Recommended order (highest impact first):

M1 · Get the changes

• git pull in HBox_PCB (see section 6).

M2 · Swap the F2 (fuse) footprint

• In the PCB: right-click F2 → Change Footprint… → Fuse:Fuseholder_Littelfuse_Nano2_154x.
• The block is 9.7 × 5 mm (was 4.5 × 3.2). Keep it near its current spot (159.5, 127), between P1 (24 V input) and Q23. Tracks /24V_IN and /VIN_FUSED ≥ 1.5 mm.
• Leave tweezer access to the fuse (it pulls straight up): nothing tall within 2 mm of its long sides.

M3 · Rebuild the U25 regulator group (24 V → 5 V) — the most important one

Problem: U25 (TPS54360B) sits 15 mm north of its power parts:

Measurement	Now	Target
Diode D34 (cathode) → U25 pin 8 (SW)	18.2 mm	≤ 4 mm
Input capacitors C149/C150 → pin 2 (VIN)	5–8 mm	≤ 3 mm
Inductor L22 (pad 1) → pin 8	25.9 mm	≤ 12 mm (L22 is big; acceptable)
SW node copper (pin 8 → D34 → L22)	0.5 mm track	polygon ≥ 2 mm, as short as possible
GND vias under U25's thermal pad	0	≥ 6 (to In1 and In2)
R120–R123, C155, C156 (compensation/FB/RT)	nearby	≤ 5 mm from pins 3–6, away from SW

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Key idea: there's no room left around U25 (the U6 charger and its parts fill the north-east). So U25 moves down to its big parts, instead of moving the big parts up.

Steps:

• Step 1 — Move C151 out (100 µF electrolytic, now at 173.75, 123.9). It's only an energy reservoir and works the same 10–20 mm away. Suggestion: rotated 90°, centred at ≈ (169.5, 112), the gap U25 leaves behind. It stays on /VIN_PROT.
• Step 2 — Put U25 where C151 was, centre ≈ (175.5, 124.5), rotated so that pin 8 (SW) is the corner closest to D34's cathode (D34's south pad, at 182.5, 126.65) and pin 2 (VIN) faces west.
• Step 3 — C149 and C150 right against pin 2 (VIN), ≤ 3 mm, with their GND end toward U25's thermal pad. This is the loop that radiates: input → U25 → D34 → GND → input. Keep it tiny.
• Step 4 — D34 stays where it is (182.5, 123.25). Its anode (GND) goes to the same GND island as C149/C150 and U25's pad.
• Step 5 — L22 stays. Join pin 8 → D34 cathode → L22 pad 1 (193.5, 126.9) with one polygon ≥ 2 mm wide. No wider than needed (this is the node that "shouts").
• Step 6 — Small parts go with U25: C152 (BOOT) between pin 1 and pin 8; R120, R121, R122, R123, C155, C156 on the pin 3–6 side (quiet side). The FB divider (R121/R122) senses 5 V at the output capacitors C153/C154, not at the inductor pad.
• Step 7 — Ground: one GND island on F.Cu under the whole group, ≥ 6 vias under U25's thermal pad, and 2–3 vias next to each capacitor GND and D34's anode.
• Step 8 — /VIN_PROT from Q23 to C149/C150: ≥ 1.5 mm (or a polygon).

!!! tip "Reference" This is the same arrangement as TI's reference layout for the TPS54360 and the v6 Copper & EMC placement guide, §2.

M4 · Same fix, smaller, on the modem regulator U20

Measurement	Now	Target
L20 (SW pad) → U20 pin 8 (SW)	7.6 mm, 23 mm track at 0.25 mm	≤ 3 mm, short track ≥ 1 mm
C127 (10 µF) → U20 pin 2 (VIN)	5.4 mm	≤ 3 mm
GND vias under U20's pad	0	≥ 4

• Move L20 next to U20 pin 8 and route /SW_MODEM short and wide.
• Move C127 next to pin 2. (C128 is already fine, at 2 mm.)
• Vias under U20's thermal pad.

M5 · Vias under the other power chips

• U6 (LTC4040 battery charger), U2 and U12 (MP1584): 0 vias under their thermal pad today. Add ≥ 4 each (the thermal pad is also their ground and their heatsink).

M6 · Widen the power tracks

Use this table (the DRC warning list is incomplete: it misses SW_BAT and the modem nets).

Priority	Net	Now	Target	Why
1	/SW_BAT	0.25 mm, 12 mm	≥ 1.0 mm or polygon	~2.5 A battery path. Already flagged critical in v5.5 (0.3 mm); v6 is thinner.
2	/VEH5V	0.25 neck + 0.5 mm, ~110 mm	≥ 1.0 mm	U25 output, up to ~3 A
3	/MAIN5V, /SYS5V	0.25–0.5 mm, 100–150 mm each	≥ 1.0 mm on the trunk	Main 5 V for the whole board
4	/BAT_PLUS	0.25–0.5 mm, 118 mm	≥ 1.0 mm	Battery current
5	/SW_MODEM	0.25 mm, 23 mm	≥ 1.0 mm and short	Solved by M4
6	/VBAT_MODEM	0.25 neck (1 mm), 0.5 (11 mm)	≥ 1.0 mm	2 A bursts when transmitting
7	/VIN_MODEM, /SW_IN, /VIN_SW	0.25–0.5 mm	≥ 0.8 mm	Regulator inputs
—	/VIN_PROT, /SW_PWRIN	0.5 mm	—	Solved by M3
No	/3V3_ETH, /5V_FAN, /SW_FAN, /FAN_RET	0.25–0.5 mm	leave	Under 0.3 A

• Priorities 1 to 7.

M7 · Close out

• Refill zones (key B) — the holes moved and the fill is stale.
• DRC → 0 errors. (Yellow track-width warnings left on the "No" nets in the table are fine.)
• Check in the 3D viewer that J14 (SIM holder) has a clear front: the card enters from one short end; confirm which on the JAE drawing and leave ~6 mm clear in front of it.
• git add + commit + push (section 6) and tell Leo.

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4. What's left — Leo

• Pre-order J14 (C2977286) into the JLC account: it's a "Pre-ordered" part; they won't place it otherwise.
• Decide J10 (RJ45), P11 and P12: fitted on this run? Today they're DNP on the PCB only.
• Review the parts where the choice matters: L20 Sunlord MWSA0804S-4R7MT (C17700167; check its pads fit the SRU8028 footprint), L21 Murata LQG18HN68NJ00D (C162555, GNSS antenna choke), C149/C150 2.2 µF 100 V (C153036), C151 Nichicon 100 µF 50 V (C116241), RS1 10 mΩ 1 W (C105362), F2 0154002.DR (C206910).

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5. JLCPCB order settings (once it's GO)

Option	Value
Layers / thickness	4 layers, 1.6 mm, stackup JLC04161H-7628
Finish	ENIG (required for the LGA modules U19 and U18)
Assembly	Standard PCBA, top side only
X-ray	Request on U19 (A7670SA) and U18 (ZED-F9P)
Pre-order	J14 C2977286 before the order
Through-hole parts	H4, J9, J11, K1, P1–P10, SW1, SW2 (16): hand-soldering on 5 boards is reasonable
Files	BOM/CPL generated from the PCB (Fabrication Toolkit). Check rotations in JLC's preview: U19, U18, J14, SOT-23s

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6. Git commands

Michelle (HBox_PCB clone):

git pull
# … work in KiCad, save …
git add hbox-watchdog-v6.kicad_pcb
git commit -m "v6 layout: U25/U20 regrouped, thermal vias, power widths, F2 holder"
git push

Leo (Drogheda project, after Michelle pushes):

cd ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad && git pull helgen main
cd ~/Documents/Claude/Projects/Drogheda && git add 03-Architecture-Hardware/kicad && git commit -m "bump kicad" && git push

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7. Change history for this audit (HBox_PCB)

Commit	What
bb78cb8 · 0288bd0	T14: J14 primary, U22 DNP, ERC errors fixed, J14 LCSC
91d2049 · 8a49327	T15: LCSC on 64 parts, JP out of BOM, SIM + U19/L22 on the PCB, dangling tracks, width warnings; library
61652cc	T16: holes 130 × 90 mm, MH5–MH8
d2db77f · 03d83d1	T17: fuse F2 → 0154002.DR holder