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title tags date project author
EinarBoard v6 — Revisión contra las lecciones de la V5.5 (26–27 sep 2026)
project-drogheda
hardware
einarboard
v6
v5.5
revision
lecciones
2026-09-28 Project Drogheda Helgen Technologies

EinarBoard v6 — Revisión contra las lecciones de la V5.5 (26–27 sep 2026)

!!! warning "Designadores de antes del 22-oct (T43)" Este documento conserva los designadores que tenía la tarjeta en su fecha. Desde el 22-oct (T43) la V5.6, la V5.7 y la v6 traen otros, y varios nombres viejos ahora son otra pieza: en la v6, U6 es ahora el módem A7670SA (antes U19) y el LTC4040 es U17 (antes U6). Para leerlo contra la tarjeta de hoy, usa la tabla viejo → nuevo; lo que ya no existía el 22-oct no está en la tabla.

!!! note "Documento histórico — superado por la auditoría completa v6 (28-sep-2026)" Revisión de solo lectura hecha la mañana del 28-sep. La auditoría completa v6 del mismo día la profundiza y supera; lo que se aplicó está en el resumen de las 3 pasadas y la lista de liberación en el plan de corrección.

!!! warning "EinarBoard v6 (hbox-watchdog-v6): en diseño, no se pide" Diseño nuevo con ZED-F9P y módem A7670SA soldados a bordo. No es la V5.6 que se manda a fabricar esta semana (hbox-watchdog-v5, zócalos para simpleRTK2B y 4G NTRIP Master). Los hallazgos marcados «Impacto en V5.6» ya se aplicaron a la V5.6 y están en su informe de cambios.

Fecha: 2026-09-28 · Diseño revisado: kicad/hbox-watchdog-v6.kicad_sch / .kicad_pcb (estado del 25-sep, después de T15) · Documentos de referencia: ECO V5.6, informe de cambios V5.6, auditoría pre-fabricación v6, CHANGELOG.md del firmware 0.5.8 → 0.6.0 · Autor: Helgen Technologies (elaborado con asistencia de Claude) · Alcance: revisión de solo lectura; no se modificó ningún archivo de KiCad. La auditoría completa v6 del mismo día profundiza y supera esta revisión; lo aplicado está en el informe de cambios v6.

Resumen ejecutivo

  1. La v6 ya resuelve por arquitectura el hallazgo más grave de la semana (F1): el módem A7670SA tiene su propio buck AP64350 (U20) con MODEM_PWR_EN en PC10, PWRKEY en PC8, STATUS en PC9 y RST en PC11, y su UART llega al MCU por USART6 (PC6/PC7). El módem se puede arrancar solo, sobre riel asentado, y se sabe si está vivo.
  2. Con eso, el ciclo de 10 min en batería (F2) y la recuperación de enlace sin matar el módem (F3) son posibles en v6: falta solo el firmware (ENABLE_DUTY 1 con la secuencia PWR_CTRL → 4 s → MODEM_PWR_EN).
  3. Cargador (F4): RS1 ya es 10 mΩ (C105362, límite 2.5 A) ✅, pero R50 sigue en 825 Ω (2.4 A) ❌ → 1.5 kΩ (C22843).
  4. Térmico del LTC4040 (F5): /SW_BAT es una pista de 0.25 mm (peor que los 0.3 mm de la V5.5), /BAT_PLUS 0.25–0.5 mm, el EP de U6 no tiene vías térmicas, L6 está a 15 mm de U6 y no hay ningún sensor de temperatura junto a U6/L6 (el TMP102 se eliminó; el SHT40 U3 está a 71 mm). ❌ — es el cambio nº 1.
  5. Ventana NTC (F6): R55 (RNTB) 10 k y JP2 puenteado a Li-ion, igual que la V5.5; la pausa a ~40–42 °C se repite en v6 hasta decidir la química (LFP-HT + JP2 2-3 + 5.6 k). CHRG_FAULT sí llega al MCU (PB4) para mostrar «pausa NTC».
  6. Fuente de 5 V (F7): U25 TPS54360B está fijada a 5.00 V (R121 53.6 k / R122 10.2 k) → solo 0.56 V sobre el PFI (4.44 V) y 0.10 V sobre la línea de corte del gobernador (4.90 V): el cargador se cortaría en cada ráfaga LTE. ❌ → R121 57.6 k (5.32 V).
  7. Robustez (F8): ESD del DFU ya está junto a J11 (3–7 mm) ✅ y ETH_INT va a PC0 (sin trampa BOOT1) ✅; pero J9 (USB del módem) no tiene ESD, ETH_RST (PA15) no tiene pull-down y no hay puente en paralelo a P5 (corte). F1 PPTC 3 A queda solo en el riel del F9P (inocuo, sobredimensionado). Sin PoE en J10 por diseño.
  8. Software (F9): la v6 pierde el $GPTXT H00xx del NTRIP Master de ArduSimple (el módem ahora es nuestro) → la identidad debe generarla el MCU ($PHID por UID, ya existe en 0.6.0-eth) también por 4G.
  9. Veredicto: 3 ✅ (F1, F2, F3) · 4 ⚠ (F4, F6, F8, F9) · 2 ❌ (F5, F7). Todos los ❌ y ⚠ son cambios de valor de BOM o de layout; ninguno cambia la arquitectura.
  10. Los cinco cambios por riesgo: (1) cobre + vías + sensor en U6/L6; (2) U25 a 5.3 V; (3) R50 1.5 k; (4) condensadores de VBAT_MODEM pegados a U19 y pistas del módem ≥ 0.8 mm; (5) pull-down en ETH_RST + USBLC6 en J9 + decidir RNTB/JP2.

Índice del cuerpo del informe

El cuerpo está en inglés. Vocabulario: finding = hallazgo · footprint = huella · track = pista · via = vía · pour = vertido de cobre · EP = pad térmico.

Sección Qué contiene
0. Method Cómo se extrajeron los datos de la tarjeta y del esquemático; mapa pad → pin del LQFP-64.
1. Lesson-by-lesson review (F1–F9) Cada lección de banco de la V5.5 contra lo que hace la v6 tal como está dibujada: módem en batería, ciclo de 10 min, recuperación de enlace, cargador, térmico del LTC4040, ventana NTC, margen de la fuente de 5 V, robustez, software.
2. Specific v6 checks requested Comprobaciones puntuales pedidas por Leo.
3. What to carry from V5.6 into v6 Qué cambios de la V5.6 deben llevarse a la v6.
4. Checklist ordered by risk Checklist por riesgo con responsable.
5. Notes and non-findings Notas y lo que se revisó y no resultó hallazgo.

Cuerpo del informe (inglés)

0. Method

  • Board: pad→net dump of every footprint (padnets2.py), track widths/lengths per net, via positions, footprint positions and pad-to-pad distances computed from hbox-watchdog-v6.kicad_pcb.
  • Schematic: symbol values, LCSC and Note properties and block texts from hbox-watchdog-v6.kicad_sch.
  • STM32F411RET6 LQFP-64 pad → pin mapping used throughout (pad 15 = PA1, 24 = PC4, 25 = PC5, 37 = PC6, 38 = PC7, 39 = PC8, 40 = PC9, 41 = PA8, 43 = PA10, 50 = PA15, 51 = PC10, 52 = PC11, 55 = PB3, 56 = PB4, 57 = PB5, 8 = PC0, 28 = PB2).
  • Ground truth for the lessons: the bench findings of 26–27 Sep on V5.5 with firmware 0.5.7–0.6.0 (F1–F9 below).

Where a fact could not be found in the v6 files, it is stated as such.

1. Lesson-by-lesson review

F1 — Modem never cold-starts on battery (shared Q1 switch, MP1584 UVLO, no MCU visibility)

What v6 does today (found in the files):

Item v6
Modem power path U20 AP64350SP-13 (C2071691), L20 4.7 µH/5 A (C17700167), output /VBAT_MODEM = 0.8 V × (1 + R110 75 k / R111 20 k) = 3.80 V. Input /VIN_MODEM fed by D20 SS34 from /24V (vehicle side, via Q10) or D21 PMEG3050EP from /MAIN5V (LTC4040 boost output on battery). The modem no longer hangs from Q1, F1 or /SW_5V.
Modem enable U20.3 EN = /MODEM_PWR_EN = U16 pad 51 = PC10, with R113 100 k to GND (modem OFF while the MCU is in reset/DFU). No series resistor (direct drive; fine for the AP64350 EN pin).
PWRKEY / RST / STATUS /MODEM_PWRKEY = PC8 (pad 39) → Q20 2N7002 open-drain → U19.1 PWRKEY, R114 100 k pull-down on the gate. /MODEM_RST = PC11 (pad 52) → Q21 2N7002 → U19.16 RESET, R115 100 k. U19.66 STATUS (1.8 V) → U24 74LVC2T45 → /MODEM_STATUS = PC9 (pad 40). U19.52 NETLIGHT only drives D4G1 via R109/Q22 — not read by the MCU (STATUS covers the need).
Modem UART visibility U19.9 TXD → U24 → /DOUT_4G → U18.26 (ZED-F9P UART2 RXD, RTCM in) and R106 100 Ω → /USART6_RX = PC7 (pad 38). U19.10 RXD ← U23 ← /DIN_4G ← K1 relay common: NC = /USART1_RX (ZED-F9P U18.27 TXD2 → also MCU PA10), NO = /USART6_TX = PC6 (pad 37). So the MCU always hears the modem's TX (RTCM byte count = "modem registered and NTRIP flowing"), and talks to it on USART6 when K1 is in Mode B. This is the RTCM_TAP of V5.6 built in.
F9P power Q1 AO3401A (gate via Q5/R1 from /PWR_CTRL = PA1, pad 15) → /SW_5V → U21 AP2112K-3.3 → /3V3_GNSS → U18. Independent of the modem.
UVLO margin on battery /MAIN5V (boost, R53 499 k / R54 100 k → 4.79 V nominal, 4.6 V measured under load on V5.5) − D21 forward drop (≈0.3–0.45 V at 1–2 A) ≈ 4.2–4.5 V at U20 VIN vs AP64350 VIN(min) 3.8 V → ≈ 0.4–0.7 V margin (V5.5 had ≈ 0.1 V). Adequate but not generous: the buck runs at ~90 % duty (3.8 V out of 4.3 V in) during a 2 A burst.
Input capacitance at U20 C127 10 µF (5.4 mm from U20.2) + C128 1 µF (2.0 mm). The V5.6 ECO specifies 2 × 22 µF + 10 µF at VIN (< 3 mm).
Output bulk at U19 C130 220 µF, C131 220 µF, C132 22 µF, C133 1 µF, C134 100 nF, C135 33 pF, C136 10 pF, D22 SMAJ5.0A. Distances from the VBAT pads (U19.55/56/57): C130 17.8–19.7 mm, C131 10.5–12.4 mm, C132 5.6–7.3 mm, C133 4.1–5.5 mm, D22 23–25 mm. The 440 µF sits 10–20 mm away, behind /VBAT_MODEM tracks of 0.25–3.0 mm (58.9 mm total, 6.3 mm on In1 at 0.5 mm).

Verdict: ✅ covered (architecture) — 4 layout/value follow-ups.

Changes:

  1. Move C131 (and ideally C130) to ≤ 5 mm of U19 pads 55–57; pour /VBAT_MODEM on F.Cu from L20 to U19 (≥ 1.5 mm, no 0.25/0.5 mm necks; the T15 DRC rule already flags ≥ 0.8 mm).
  2. Add 2 × 22 µF 0805 (C86817) at U20.2 VIN (< 3 mm), keep C127/C128; widen /VIN_MODEM (0.25/0.5 mm today) and /SW_MODEM (0.25 mm, 23 mm long) to ≥ 0.8 mm.
  3. Battery-mode headroom (choose one, bench-decided): (a) R53 499 k → 511 k (C188257) → boost 4.89 V (+0.1 V at U20 VIN); (b) replace D21 with a low-Vf Schottky in a bigger package or a P-FET ideal-diode; (c) lower /VBAT_MODEM to 3.6 V (R110 75 k → 70 k) — A7670SA VBAT range is 3.4–4.2 V, 3.8 V typical; 3.6 V keeps the buck out of dropout. Not required to order; required before the 20-cycle battery test.
  4. Firmware (v6 board_v6.h): PIN_MODEM_PWR_EN PC10, PIN_MODEM_PWRKEY PC8, PIN_MODEM_STATUS PC9, PIN_MODEM_RST PC11, modem UART = USART6 (PC6 TX / PC7 RX); K1 Mode B via BYP_CTRL = PB5 (pad 57, R40 → Q6 → K1 coil).

Note on behaviour: because R113 is a pull-down, any MCU reset (DFU, IWDG, NVIC_SystemReset) drops MODEM_PWR_EN and power-cycles the modem. That is the intended V5.6 policy (modem OFF while the MCU is not in control), but firmware must re-run the settled-rail sequence after every reset, and a watchdog reset costs a ~30 s re-registration.

F2 — 10-min duty cycle on battery impossible on V5.5

What v6 does today: /PWR_CTRL (PA1) switches only the F9P rail (Q1 → /SW_5V → U21); /MODEM_PWR_EN (PC10) switches only the modem buck. /MODEM_STATUS (PC9) and the RTCM tap on PC7 give a real "modem up" signal. NRST reaches only the MCU (SW1, P6 RESET-EXT, TP5, C104), as on V5.5.

Verdict: ✅ covered (hardware). Firmware: ENABLE_DUTY 1 on the v6 build with the V5.6 window — PWR_CTRL high → ≥ 4 s → MODEM_PWR_EN high → PWRKEY pulse → wait STATUS high / first RTCM bytes on PC7 → ≥ 2 $PHLG with pwr=BATT and fresh fix → MODEM_PWR_EN low → PWR_CTRL low → sleep 10 min. End of window decided by STATUS/RTCM, not by a timer. Note K1 (G5V-1, coil on /SYS5V via Q6) draws its 0.15 W whenever Mode B is held on battery.

F3 — Link-recovery stack cycles on battery kill the modem

What v6 does today: the modem can be reset (MODEM_RST PC11), PWRKEY-cycled (PC8) or power-cycled alone (MODEM_PWR_EN PC10) without touching the F9P, and MODEM_STATUS (PC9) confirms the result.

Verdict: ✅ covered (hardware). Firmware rule for v6 stays as 0.5.9: no stack cycle on battery, ever; recovery escalates modem-only — MODEM_RST 500 ms → PWRKEY off/on → MODEM_PWR_EN OFF 5 s / ON — and only after PWR_CTRL has been high ≥ 4 s. Never cycle PWR_CTRL for a link problem.

F4 — Charger input limit above the supply (RS1 8 mΩ), charge current 2.4 A (R50 825 Ω)

What v6 does today: RS1 = 10 mΩ/1 % 1206 (C105362) between /VEH5V and /VIN_SW → LTC4040 input limit 25 mV / 10 mΩ = 2.5 A ✅, below U25's 3 A. R50 = 825 Ω/1 % (C50214) on PROG → 2000/825 = 2.42 A charge ❌. CHRG_EN = PA8 (pad 41) with R56 100 k pull-down — the 0.6.0 governor works unchanged. CHRG_STAT = PB3, CHRG_FAULT = PB4 (pull-ups R57/R58 100 k).

Verdict: ⚠ partial. Change: R50 825 Ω → 1.5 kΩ 0603 1 % (C22843) → 1.33 A (12 Ah in ~9 h). Governor 0.6.0 stays as the second layer. On v6 the supply is U25 (3 A rated, 3.5 A switch) — same reasoning as the SD-15B.

F5 — Slow charge on H0008: LTC4040 die-temperature cycling from thin copper / no thermal vias

What v6 does today (measured on the board file):

Item v6 Target (ECO D2 / Copper Plan)
/SW_BAT (U6.21/22 → L6.1) 4 segments, 0.25 mm, 12.3 mm total, F.Cu, no pour ≥ 2 mm polygon
/BAT_PLUS (P3.1 → L6.2 → U6.23, C35, R5) 0.25 mm (5.4 mm) + 0.5 mm (42 mm F.Cu + 70.5 mm In2) + 1.0 mm (4.9 mm); 2 vias; no pour ≥ 1.5 mm + via farm
U6 exposed pad (pad 25, 2.65 × 3.65 mm) footprint QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm (no ThermalVias variant); 0 vias inside the EP; nearest GND via 4.4 mm away ≥ 9 thermal vias to In1 GND
L6 2.2 µH/8 A distance to U6 15.2 mm (pad-to-pad 10.2–11.1 mm) ≤ 5 mm
Input cap C30 10 µF / C31 2.2 µF to U6 11.2 mm / 10.0 mm ≤ 3 mm
Temperature sensor at U6/L6 None. U4 TMP102 was deleted in v6 (schematic note); U3 SHT40 is at (122.4, 77.3), 71 mm from U6; P7 NTC-HOTSPOT / P8 NTC-PROBE-2 are JST jacks for external probes (PB1 / PC4) at 100 mm. On-board sensor at U6/L6

Verdict: ❌ missing. This is the highest-risk item: v6 repeats the V5.5 boost copper and makes it slightly worse (0.25 vs 0.3 mm), and the charger will run its ~2.5 A input / 1.3–2.4 A charge through it at 45 °C ambient.

Changes:

  1. Re-cluster U6: L6 ≤ 5 mm from pads 21/22, C30/C31 ≤ 3 mm from pads 6/16, C35 at pad 23 (pre-fab audit B5).
  2. /SW_BAT as an F.Cu polygon ≥ 2 mm wide; /BAT_PLUS ≥ 1.5 mm F.Cu from P3 to L6/U6 with a via farm to an In2 copper area (drop the 70 mm 0.5 mm inner run).
  3. Replace the U6 footprint with the …_ThermalVias variant or add ≥ 9 × 0.3 mm vias in the EP to the In1 GND plane; keep the In1 plane solid under U6 (it is split into islands today — pre-fab audit §7).
  4. Add a temperature sensor at U6/L6: TMP102 SOT-563 (C99269, address 0x48 — free on v6; SC16IS752 is 0x4D, SHT40 0x44, SC7A20 0x18) placed between U6 and L6, or an on-board 10 k NTC to PC5 (pad 25, ADC1_IN15, free) with the same 10 k/100 nF network as R42/C24. Firmware: tchg append field in $PHLG; governor uses it instead of the V5 U4 cell sensor. Also log tmax.
  5. Bench: thermal camera on U6/L6 during 1 h of charge at 1.3 A and 1 h of backup at 2.5 A; the 60 mV/30 s pulsing seen on H0008 must not appear.

F6 — NTC pause invisible; charge window with RNTB 10 k pauses above ~40–42 °C

What v6 does today: R55 (= RNTB) 10 k/1 % (C25804) from /VEH5V to /NTC (U6.17, P3.3). JP2 value F2:Li-ion, bridged 1-2 → /F2_SEL = /MAIN5V (high) = Li-ion 4.0/4.1 V float. JP3 F1:0, JP4 F0:1 as on V5.5. CHRG_FAULT → PB4 with pull-up: the firmware can show cflt=1 as "pausa NTC" (LTC4040 keeps CHRG low during an NTC pause; only FAULT goes low).

Verdict: ⚠ partial (visibility ✅, window ❌ until the chemistry decision).

Changes (BOM/solder-jumper only, PCB unchanged): if LFP-HT 26650 is chosen (ECO D1a): JP2 2-3 (F2 low, 3.50 V float) + R55 5.6 k with a B3380 NTC (window +10…+60 °C). If Li-ion stays: keep 10 k and accept the pause (or 6.6 k = pause at 55 °C, hard on the cell). Firmware/monitor: ltc=PAUSA NTC when CHRG_EN allowed ∧ CHRG_STAT idle ∧ CHRG_FAULT low; cell-temperature inhibit threshold per chemistry (Li-ion 45 °C / LFP 55–60 °C). Silkscreen JP2 = F2 (Li-ion / LFP).

F7 — Power-supply margin: 5.25–5.57 V trimmed units vs PFI 4.44 V / warning 4.60 V / shed 4.90 V

What v6 does today: U25 TPS54360B (C524806), feedback R121 53.6 k/1 % / R122 10.2 k/1 % → V_out = 0.8 V × (1 + 53.6/10.2) = 5.00 V (pre-fab audit: "5.00 V, ~620 kHz"; R120 162 k). R124 523 k / R125 84.5 k (EN UVLO divider) are DNP → EN floats high (internal pull-up), U25 runs from ≈ 4.5 V input. LTC4040: PFI R51 270 k / R52 100 k → 1.2 V × 3.7 = 4.44 V; boost R53 499 k / R54 100 k → 0.8 V × 5.99 = 4.79 V. 5V_SENSE = /VEH5V × 10 k/(10 k + 10 k) (R7/R8) → PA4, so the ADC scale is fine up to 6.6 V. P2 (bench SD-15B) is in parallel on /VEH5V ("one source at a time").

Margins with 5.00 V: to PFI 0.56 V; to the 0.6.0 governor shed line (4.90 V) 0.10 V; to the governor start line (5.05 V) −0.05 V — the charger would never be enabled, and a 100–200 mV LTE sag (V5.5 measured) would hit the shed line on every burst.

Verdict: ❌ missing.

Changes: R121 53.6 k → 57.6 k/1 % 0603 → 0.8 × (1 + 57.6/10.2) = 5.32 V (56.2 k → 5.21 V is the minimum acceptable). Within LTC4040 VIN range (3.5–5.5 V) and U25 rating; 5V_SENSE unchanged. Pick the LCSC number in the sourcing pass (basic 0603 1 %). Governor thresholds (5.05 start / 4.90 shed / 4.60 warn / 4.44 PFI) then have the same 0.3–0.9 V ladder as the field units. Also re-cluster U25 (L22 25.9 mm, D34 18–23 mm, C149/C150 5.4–8.8 mm from pins today) — pre-fab audit B5.

F8 — Robustness items (F1 PPTC, ETH_RST float, J9 ESD, DFU ESD placement, BOOT1 trap, PoE)

Item v6 today Verdict Change
F1 PPTC 3 A (C20627123) F1 between /SYS5V and /SW_IN → Q1 → /SW_5V → U21 LDO → F9P only (/SW_5V nodes: Q1.3, C3, C40, C119, U21). The modem is not behind it. ⚠ Harmless (≈ 15 mV at 150 mA) but pointless at 3 A; resize to 1–1.5 A hold so it actually protects the F9P/LDO, or keep and note. Not a blocker.
ETH_RST (PA15, pad 50 → U11.37) Only two nodes; no pull resistor. U12 (3V3_ETH buck) has EN tied to VIN (U12.2 = /SYS5V) → /3V3_ETH is always up, on battery too. During an MCU reset PA15 floats, the W5500 leaves reset and draws ~130 mA for the ~4 s. ❌ Add 100 k 0603 (C103211) ETH_RST → GND (= V5.6 R112). Optional: drive U12 EN from a free MCU pin (PD2 pad 54 or PB10 pad 29) with a 100 k pull-down so /3V3_ETH is fully off on battery and in reset.
J9 modem USB-C ESD /USB_DP, /USB_DM, /USB_VBUS nodes: J9 and U19 only. No ESD device. Rcc1/Rcc2 5.1 k present. ❌ Add USBLC6-2SC6 SOT-23-6 (C7519) at J9 (= V5.6 D19): I/O1 → USB_DM, I/O2 → USB_DP, VBUS → USB_VBUS.
DFU ESD at J11 D14 (DFU_DP) 3.0 mm, D15 (DFU_DM) 3.7 mm, D16 (DFU_VBUS) 6.6 mm from J11 centre. ✅ —
BOOT1 trap ETH_INT = PC0 (pad 8); PB2 (pad 28) = /BOOT1_STRAP with R99 10 k to GND; schematic note "never repurpose PB2". ✅ —
PoE on J10 J10 HR911105A pins 7/8 unconnected; no PoE PD circuit. Firmware 0.6.0-eth documents "sin PoE". ⚠ (decision) Keep no PoE (external splitter). Record the decision; if PoE is ever wanted it is a v6.1 feature (PD controller + isolated DC-DC), not a patch.
Cutoff bypass P5 CUTOFF-SW between /MAIN5V and /SYS5V; no solder-jumper in parallel (JP1 = fan, JP5 = RS-485 term). ⚠ Add JP_CUT (SolderJumper_2_Open) across P5, open by default (= V5.6 JP6).
Silkscreen Not checked here (pre-fab audit: all labels 0.5 mm/0.1 mm). — SW1 = RESET MCU, JP2 = F2 (Li-ion / LFP), P5 = CUTOFF, labels ≥ 0.8/0.15 mm.

Verdict: ⚠ partial.

F9 — Software/process lessons

Lesson v6 implication Verdict
Unit identity = modem $GPTXT H00xx v6 has no ArduSimple NTRIP Master: the A7670SA is driven by the MCU, so nobody emits $GPTXT H00xx. The MCU must generate the identity on every path (4G and Ethernet) — $PHID,<uid>,<fw>,<board>,<mac>,<up_s> from 0.6.0-eth is the right vehicle; the server (retranslator) needs to accept $PHID as the primary ID before v6 ships. ⚠
$PHLG append-only fields New v6 fields (tchg, rtcm_bps, modem_status, tmodem if read from the module) go at the end. ✅ (rule)
Deploy with conflict markers broke the dashboard Process: pre-deploy syntax check (node --check / python -m py_compile) in the deploy script; never git stash pop on the production tree. Not a board item. ⚠ (process)
Monitor shows power source and charger state explicitly; history stores pwr, v5min, vbat_min v6 adds MODEM_STATUS and CHRG_FAULT (PB4) → columns "Módem" and "pausa NTC". ✅ (rule)
Modem temperature v6 can read it from the module over USART6 (AT+CPMUTEMP on SIMCom A76xx, to be confirmed on the A7670SA firmware) — no extra sensor needed for the modem; the charger sensor (F5) is still needed. —

Verdict: ⚠ partial (identity path must change for v6).

2. Specific v6 checks requested

Check Found in v6 Assessment
U25 output divider and margin to PFI / VSYS R121 53.6 k / R122 10.2 k → 5.00 V; PFI 4.44 V (R51 270 k / R52 100 k); boost 4.79 V (R53 499 k / R54 100 k) ❌ 0.56 V to PFI, 0.10 V to the 4.90 V shed line → R121 57.6 k (5.32 V)
Modem buck input on battery and UVLO margin /VIN_MODEM ← D21 PMEG3050EP ← /MAIN5V (boost) on battery; ← D20 SS34 ← /24V on vehicle power ⚠ ≈ 4.2–4.5 V at U20 VIN vs 3.8 V min → 0.4–0.7 V; improve with R53 511 k, lower-Vf D21 or VBAT_MODEM 3.6 V
MODEM_PWR_EN / PWRKEY / STATUS / RST to MCU PC10 (pad 51) / PC8 (39, via Q20) / PC9 (40, via U24) / PC11 (52, via Q21); pull-downs R113/R114/R115 100 k ✅
Modem UART to MCU USART6: PC7 RX ← R106 100 Ω ← /DOUT_4G (always); PC6 TX → K1 NO → /DIN_4G (Mode B) ✅
Modem VBAT bulk near U19 440 µF (C130/C131) at 10.5–19.7 mm from pads 55–57; C132 22 µF at 5.6–7.3 mm ⚠ move to ≤ 5 mm, pour VBAT_MODEM
/SW_BAT and /BAT_PLUS copper 0.25 mm × 12.3 mm; 0.25–0.5 mm (+70 mm on In2); no pours ❌
LTC4040 EP thermal vias 0 in the EP; footprint has no ThermalVias variant ❌
RNTB and JP2 default R55 10 k; JP2 1-2 = Li-ion ⚠ pending D1
F1 / F2 fuses F1 PPTC 3 A on the F9P rail only; F2 2 A/125 V nano fuse in holder on /24V_IN (LCSC still TBD per pre-fab audit) ⚠ resize F1 (optional); pick F2 part
ETH_RST pull none ❌ 100 k to GND
J9 / J11 ESD J11 ✅ (D14/D15/D16 at 3–7 mm); J9 ❌ none add USBLC6-2SC6 at J9
W5500 PoE none (J10 pins 7/8 open) decision: stay without PoE
Switcher EP vias (U20, U25) 0 vias within 3 mm of either EP add thermal vias (secondary to U6)

3. What to carry from V5.6 into v6

V5.6 item Already in v6? Action for v6
MODEM_EN sequencing (F9P first, modem 4 s later on a settled rail) Hardware ✅ (MODEM_PWR_EN PC10 + PWR_CTRL PA1) Firmware board_v6.h + ENABLE_DUTY 1; identical window logic to V5.6 0.7.0, plus PWRKEY pulse and STATUS wait.
RTCM / modem-UART visibility (RTCM_TAP PC7 = USART6_RX) ✅ built in (R106 → PC7; K1 → PC6) Byte counter on USART6 RX = "NTRIP flowing"; rtcm_bps field.
Thermal copper for U6 (ECO D2 / EMC #1 #2) ❌ /SW_BAT ≥ 2 mm pour, /BAT_PLUS ≥ 1.5 mm + vias, EP ≥ 9 vias, L6/C30 re-clustered.
RS1 10 mΩ (C105362) ✅ —
R50 1.5 k (C22843) ❌ (825 Ω) Change value.
RNTB 5.6 k + JP2 2-3 (if LFP) ❌ (10 k, Li-ion) Decide chemistry (D1); BOM/jumper only.
PSU set-point ≥ 5.2 V ❌ (5.00 V) R121 57.6 k → 5.32 V.
ESD at connectors J11 ✅ / J9 ❌ USBLC6-2SC6 (C7519) at J9.
Fuse in the F9P rail ⚠ (3 A PPTC) Resize to 1–1.5 A or leave; document.
ETH_RST pull-down 100 k ❌ Add (C103211).
PoE decision none by design Keep; write it in the schematic block-N note.
Second TMP102 / NTC at U6 ❌ (no sensor near U6; TMP102 deleted in v6) TMP102 SOT-563 (C99269, 0x48) between U6 and L6, or NTC → PC5.
JP_CUT across the cutoff connector ❌ Solder jumper across P5.
220 µF polymer on the F9P rail (C3) C3 47 µF elco on /SW_5V Optional on v6: /SW_5V only feeds the AP2112K LDO now.
2 × 22 µF + 10 µF at the modem buck input C127 10 µF + C128 1 µF Add 2 × 22 µF (C86817) at U20.2.
AP64350 compensation (Rcomp 14 k, Ccomp 3.3 nF, 47 pF, RT 200 k, BST 100 nF) v6 is the source (R116 14 k, C141 3.3 nF, C142 47 pF, R117 200 k, C129 100 nF) Verify against the AP64350 datasheet application table for 3.8 V / 4.7 µH / 2 × 220 µF + 22 µF (same open point as V5.6 §6.1).

4. Checklist ordered by risk

# Risk Lesson Item Refdes / value / net Owner
1 🔴 F5 LTC4040 copper + thermal vias + re-cluster /SW_BAT 0.25 → ≥ 2 mm pour; /BAT_PLUS ≥ 1.5 mm + via farm; U6 EP ≥ 9 × 0.3 mm vias; L6 ≤ 5 mm; C30/C31 ≤ 3 mm Michelle
2 🔴 F7 Vehicle PSU set-point R121 53.6 k → 57.6 k/1 % (5.32 V); re-cluster L22/D34/C149/C150 Leo (value) / Michelle (layout)
3 🔴 F4 Charge current R50 825 Ω → 1.5 k/1 % (C22843) Leo
4 🟠 F1 Modem rail integrity on battery C130/C131 ≤ 5 mm from U19.55–57; pour /VBAT_MODEM; /VIN_MODEM, /SW_MODEM ≥ 0.8 mm; + 2 × 22 µF at U20.2; optional R53 511 k / D21 low-Vf / VBAT 3.6 V Michelle / Leo
5 🟠 F5 Temperature sensor at the charger TMP102 SOT-563 (C99269, 0x48) between U6 and L6 + 100 nF, or NTC → PC5 Leo
6 🟠 F8 W5500 in reset while MCU resets 100 k (C103211) /ETH_RST → GND; optional U12 EN from PD2/PB10 Leo
7 🟠 F8 Modem USB ESD USBLC6-2SC6 (C7519) at J9 Leo
8 🟠 F6 NTC window / chemistry R55 10 k → 5.6 k + JP2 2-3 if LFP-HT; else keep and display "pausa NTC" Leo (decision D1)
9 🟡 F8 Cutoff bypass JP_CUT solder jumper across P5 Michelle
10 🟡 F8 F9P rail fuse F1 3 A PPTC → 1–1.5 A hold (or document) ; F2 part number (TBD) Leo
11 🟡 F9 Identity without $GPTXT $PHID from MCU UID on 4G too; server accepts it Firmware / backend
12 🟡 F1/F2/F3 Firmware v6 board_v6.h pins (PC10/PC8/PC9/PC11, USART6, PB5 K1), duty window, modem-only recovery, no stack cycle on battery Firmware
13 🟡 F8 PoE Record "no PoE, external splitter" in block N Leo
14 ⚪ F1 AP64350 compensation vs datasheet table R116/C141/C142/R117/C129 Leo
15 ⚪ F5 Bench validation Thermal camera U6/L6 at 1.3 A charge and 2.5 A backup, 1 h each; 20 battery duty cycles; U20 VIN scope at 3.5 V cell Jesús / Leo

Tally: ✅ 3 (F1, F2, F3) · ⚠ 4 (F4, F6, F8, F9) · ❌ 2 (F5, F7).

5. Notes and non-findings

  • The v5.5 DzG1 gate-clamp fix, the R51 270 k PFI choice (E-PFI 24-Jul) and the RS1 10 mΩ are already in v6.
  • U12 (3V3_ETH, MP1584EN from /SYS5V) keeps the MP1584 UVLO issue but Ethernet is not used on battery; firmware 0.6.0-eth holds the W5500 in reset without 5 V. Combined with the ETH_RST pull-down that is acceptable for v6.
  • C3 47 µF and C40 22 µF on /SW_5V now only buffer the AP2112K LDO input; the V5.6 polymer upgrade is optional here.
  • Free MCU pins after this review: PC5 (25, ADC), PB10 (29), PA9 (42), PD2 (54). PC5 is the natural home for an on-board charger NTC; PD2/PB10 for a U12 EN.
  • Nothing in this review changes the v6 architecture; every item is a value, a footprint or a layout change, so the pre-fab audit's B5/B6 pass (Michelle) can absorb items 1, 2 (layout part), 4 and 9 in one go.

Ver también: manual v6 · mapa de pines MCU v6.

Historial de revisiones

Versión Fecha Cambios
1.0 2026-09-28 Revisión original (inglés) con resumen ejecutivo en español.
1.1 2026-09-29 Resumen en español al frente, índice del cuerpo, enlaces. Sin cambios técnicos.