v6 cluster placement (submodule c7d2552) + Copper Plan update
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
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<p class="sub">Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.</p>
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<p class="sub">Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.</p>
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<div class="warn"><b>Before placing anything:</b> run <i>Update PCB from Schematic</i> once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit <code>ba70f62</code>), and the sync re-nets <code>P18</code>/<code>R126</code>/<code>C157</code> to a clean <code>/NTC2</code>. Tick <i>“delete footprints with no symbol”</i> in that dialog.</div>
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<div class="warn"><b>Before placing anything:</b> run <i>Update PCB from Schematic</i> once more. The NTC2 label was sitting on PA7 (TIMEPULSE) and merged the nets — it is fixed in the schematic (commit <code>ba70f62</code>), and the sync re-nets <code>P18</code>/<code>R126</code>/<code>C157</code> to a clean <code>/NTC2</code>. Tick <i>“delete footprints with no symbol”</i> in that dialog.</div>
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<div class="note"><b>Known leftovers from the auto-clustering:</b> ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — <code>L2</code>/<code>D2</code> (under U19's new outline), <code>L6</code>/<code>DB2</code>/<code>DB3</code>/<code>Q2</code>/<code>Dbk1</code> near U25, <code>C40</code>, <code>R40</code>/<code>R41</code> at Y3. Drag those few aside first and the board is clean.</div>
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<h2><span class="no">§0</span>Three laws that decide EMC at placement time</h2>
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<h2><span class="no">§0</span>Three laws that decide EMC at placement time</h2>
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<div class="laws">
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<div class="laws">
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<div class="law"><b>Aggressors far from victims</b><p>Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.</p></div>
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<div class="law"><b>Aggressors far from victims</b><p>Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.</p></div>
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</div>
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</div>
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<h2><span class="no">§1</span>Suggested floorplan</h2>
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<h2><span class="no">§1</span>Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)</h2>
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<figure>
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<figure>
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<svg viewBox="0 0 700 480" style="max-width:100%;height:auto" role="img" aria-label="Suggested floorplan of the 140 by 100 mm board">
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<svg viewBox="0 0 700 500" style="max-width:100%;height:auto" role="img" aria-label="Current floorplan of the 140 by 100 mm board">
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<rect x="30" y="30" width="630" height="420" fill="none" stroke="var(--ink)" stroke-width="2"/>
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<rect x="30" y="40" width="630" height="450" fill="none" stroke="var(--ink)" stroke-width="2"/>
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<text x="30" y="20" font-size="12" fill="var(--ink2)">140 × 100 mm · connectors on the top (harness) edge · antennas leave at opposite ends</text>
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<text x="30" y="28" font-size="12" fill="var(--ink2)">140 × 100 mm · as clustered on 03-Sep (commit c7d2552) · N = top of the KiCad screen</text>
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<!-- connector strip -->
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<!-- NW ETH -->
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<rect x="32" y="32" width="626" height="34" fill="var(--plane-soft)"/>
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<rect x="32" y="42" width="200" height="130" fill="var(--plane-soft)"/>
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<text x="345" y="53" font-size="12" text-anchor="middle" fill="var(--plane)">HARNESS EDGE — P1 24V · P2 5V bench · P4 batt · P6 fan · P12/P18 NTC · P15/P16 serial · J10 ETH · J9/J11 USB</text>
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<text x="42" y="64" font-size="13" fill="var(--plane)">NW — ETHERNET</text>
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<!-- power entry -->
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<text x="42" y="81" font-size="11" fill="var(--ink2)">J10 RJ45 · U11/U12 · Y1</text>
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<rect x="32" y="66" width="180" height="120" fill="var(--copper-soft)"/>
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<text x="42" y="96" font-size="11" fill="var(--ink2)">C90–C103 · J11 USB-DFU</text>
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<text x="42" y="86" font-size="13" fill="var(--copper)">POWER ENTRY</text>
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<!-- NE LTE -->
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<text x="42" y="104" font-size="11" fill="var(--ink2)">F2 Q23 D32 → U25 buck</text>
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<rect x="440" y="42" width="218" height="200" fill="var(--copper-soft)"/>
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<text x="42" y="119" font-size="11" fill="var(--ink2)">L22 · C149–C154</text>
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<text x="452" y="64" font-size="13" fill="var(--copper)">NE — LTE ISLAND</text>
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<text x="42" y="140" font-size="11" fill="var(--ink2)">then U6 LTC4040 + RS1</text>
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<text x="452" y="81" font-size="11" fill="var(--ink2)">U20 buck+L20 · VBAT bank</text>
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<text x="42" y="155" font-size="11" fill="var(--ink2)">C30/31/78 · C32/33/34</text>
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<text x="452" y="96" font-size="11" fill="var(--ink2)">U19 A7670SA · K1 · shifters</text>
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<text x="452" y="111" font-size="11" fill="var(--ink2)">J13 U.FL → NE corner</text>
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<!-- MCU -->
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<!-- MCU -->
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<rect x="250" y="150" width="200" height="160" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
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<rect x="250" y="90" width="170" height="150" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
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<text x="350" y="175" font-size="13" text-anchor="middle" fill="var(--ink)">MCU U16</text>
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<text x="335" y="115" font-size="13" text-anchor="middle" fill="var(--ink)">MCU U16</text>
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<text x="350" y="192" font-size="11" text-anchor="middle" fill="var(--ink2)">C104–C116 · Y3/Y4</text>
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<text x="335" y="132" font-size="11" text-anchor="middle" fill="var(--ink2)">crystals · VCAP · VDDA</text>
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<text x="350" y="207" font-size="11" text-anchor="middle" fill="var(--ink2)">sense RCs C5/7/9/24/157</text>
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<text x="335" y="147" font-size="11" text-anchor="middle" fill="var(--ink2)">sense RCs · U10/Y2 below</text>
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<!-- ETH -->
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<!-- SW GNSS -->
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<rect x="470" y="66" width="130" height="100" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
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<rect x="32" y="255" width="200" height="233" fill="var(--plane-soft)"/>
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<text x="535" y="90" font-size="12" text-anchor="middle" fill="var(--ink)">ETH U11/U12</text>
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<text x="42" y="277" font-size="13" fill="var(--plane)">SW — GNSS ISLAND</text>
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<text x="535" y="106" font-size="11" text-anchor="middle" fill="var(--ink2)">C90–C103 · Y1</text>
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<text x="42" y="294" font-size="11" fill="var(--ink2)">U21 LDO · C119–C124</text>
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<text x="535" y="121" font-size="11" text-anchor="middle" fill="var(--ink2)">tight to J10</text>
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<text x="42" y="309" font-size="11" fill="var(--ink2)">U18 F9P · L21 bias tee</text>
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<!-- GNSS -->
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<text x="42" y="324" font-size="11" fill="var(--ink2)">C143/144/145 · D27 · J12 → W edge</text>
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<rect x="32" y="300" width="190" height="148" fill="var(--plane-soft)"/>
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<text x="42" y="345" font-size="11" fill="var(--ink2)">U26 accel at MH6 (SW hole)</text>
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<text x="42" y="322" font-size="13" fill="var(--plane)">GNSS ISLAND</text>
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<text x="42" y="366" font-size="11" fill="var(--crit)">quiet corner — no switchers</text>
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<text x="42" y="339" font-size="11" fill="var(--ink2)">U18 F9P · U21 LDO</text>
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<!-- SE power -->
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<text x="42" y="354" font-size="11" fill="var(--ink2)">C119–C124 · C143/144/145</text>
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<rect x="440" y="290" width="218" height="198" fill="var(--copper-soft)"/>
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<text x="42" y="369" font-size="11" fill="var(--ink2)">L21 bias tee · D27 · J12 ↓</text>
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<text x="452" y="312" font-size="13" fill="var(--copper)">SE — POWER ENTRY</text>
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<text x="42" y="392" font-size="11" fill="var(--crit)">quiet corner — no switchers</text>
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<text x="452" y="329" font-size="11" fill="var(--ink2)">P1 24V · F2 Q23 D32 · 24V parts</text>
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<!-- LTE -->
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<text x="452" y="344" font-size="11" fill="var(--ink2)">U25 + L22 + C149–C154</text>
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<rect x="480" y="200" width="178" height="248" fill="var(--copper-soft)"/>
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<text x="452" y="359" font-size="11" fill="var(--ink2)">U6 LTC4040 + RS1 · fan U2 above</text>
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<text x="492" y="222" font-size="13" fill="var(--copper)">LTE ISLAND</text>
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<text x="452" y="374" font-size="11" fill="var(--ink2)">J9 USB · RS232 U15 just west</text>
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<text x="492" y="239" font-size="11" fill="var(--ink2)">U20 buck · L20 · C127–129</text>
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<!-- diagonal separation -->
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<text x="492" y="254" font-size="11" fill="var(--ink2)">U19 A7670SA</text>
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<line x1="235" y1="370" x2="500" y2="130" stroke="var(--crit)" stroke-dasharray="6 5"/>
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<text x="492" y="269" font-size="11" fill="var(--ink2)">VBAT bank C130–C136</text>
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<text x="368" y="262" font-size="11" text-anchor="middle" fill="var(--crit)" transform="rotate(-42 368 262)">GNSS ↔ LTE on the diagonal · antennas ≥ 20 cm at the enclosure</text>
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<text x="492" y="284" font-size="11" fill="var(--ink2)">U22 SIM · U23/24 shift</text>
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<text x="492" y="299" font-size="11" fill="var(--ink2)">J13 → edge</text>
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<!-- separation arrow -->
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<line x1="225" y1="392" x2="475" y2="392" stroke="var(--crit)" stroke-dasharray="6 5"/>
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<text x="350" y="384" font-size="11" text-anchor="middle" fill="var(--crit)">RF islands at opposite ends · antennas ≥ 20 cm at the enclosure</text>
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<!-- accel -->
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<circle cx="250" cy="430" r="5" fill="var(--copper)"/>
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<text x="262" y="434" font-size="11" fill="var(--ink2)">U26 accel ≤ 10 mm from a mounting hole</text>
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</svg>
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</svg>
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<figcaption>A proposal, not a constraint — keep the two RF islands at opposite ends and the power entry beside P1/P2, and the rest is yours to optimize.</figcaption>
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<figcaption>The clustered state after commit <code>c7d2552</code> — your anchors kept (J10, P1, U18, U16, U6, U15, K1, connectors), 160 support parts packed by family. Fine-tune freely inside each region; keep the diagonal.</figcaption>
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</figure>
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</figure>
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<h2><span class="no">§2</span>Vehicle power entry — U25 TPS54360B <span class="tag">hot loop</span></h2>
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<h2><span class="no">§2</span>Vehicle power entry — U25 TPS54360B <span class="tag">hot loop</span></h2>
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<tr><td>C143</td><td>100 nF RF</td><td>DC block</td><td>inline in the 50 Ω run between L21 tap and J12</td></tr>
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<tr><td>C143</td><td>100 nF RF</td><td>DC block</td><td>inline in the 50 Ω run between L21 tap and J12</td></tr>
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<tr><td>D27</td><td>ESD9L (≤0.5 pF)</td><td>J12</td><td>at the connector, stub-less tap on the RF line</td></tr>
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<tr><td>D27</td><td>ESD9L (≤0.5 pF)</td><td>J12</td><td>at the connector, stub-less tap on the RF line</td></tr>
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</table></div>
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</table></div>
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<p>This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm; nothing but solid In1 ground under the module and the RF run. <code>TIMEPULSE</code> to the MCU is the one digital line that leaves — route it away from the RF path.</p>
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<p>This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. <code>TIMEPULSE</code> to the MCU is the one digital line that leaves — route it away from the RF path.</p>
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<h2><span class="no">§6</span>MCU core — U16 <span class="tag q">analog care</span></h2>
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<h2><span class="no">§6</span>MCU core — U16 <span class="tag q">analog care</span></h2>
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<div class="tblwrap"><table>
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<div class="tblwrap"><table>
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<h2><span class="no">§9</span>Order of work from here</h2>
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<h2><span class="no">§9</span>Order of work from here</h2>
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<ol class="steps">
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<ol class="steps">
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<li><b>Update PCB from Schematic</b> (NTC2 re-net), then place by §1–§8. Field connectors on one edge — every cable is an antenna, and one entry edge keeps their common-mode currents off the board.</li>
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<li><b>Update PCB from Schematic</b> (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.</li>
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<li><b>Say the word and I re-add the four zones</b> — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.</li>
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<li><b>Say the word and I re-add the four zones</b> — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.</li>
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<li><b>Route in this order:</b> ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.</li>
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<li><b>Route in this order:</b> ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.</li>
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<li><b>Refill zones, full DRC</b>, then the G2 external review checkpoint before ordering.</li>
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<li><b>Refill zones, full DRC</b>, then the G2 external review checkpoint before ordering.</li>
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<li><b>Bench items carried forward:</b> measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.</li>
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<li><b>Bench items carried forward:</b> measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.</li>
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</ol>
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</ol>
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<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · generated 02-Sep-2026 from the live netlist (commit <code>ba70f62</code>).</p>
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<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · updated 03-Sep-2026 to the clustered layout (commits <code>ba70f62</code> · <code>c7d2552</code>).</p>
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</div>
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</div>
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@ -1 +1 @@
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Subproject commit ba70f62b5e26577c1572912ffdbbb52b0f74093f
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Subproject commit c7d25524a7f6ec2a579be615140f45c2ac064bc3
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