MkDocs Material (ES) con el subconjunto curado de procedimientos de banco,
montaje, diagnostico y guias git; deploy privado al servidor Helgen
(nginx + htpasswd). Repo: Helgen-Services/hbox-docs -> 01dc30c
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
scripts/2026-09-15_v6_T12_sim_dual_footprint.py moves the U22 edits into the
T-script chain. Idempotent, dry-run by default, .T12bak backups, UUID invariant
guard, and a gate-0 assertion on the MFF2 land pattern. Verified to reproduce the
hand edits byte-for-byte. Part 2 (nano-SIM holder + 0R selects) pending the
holder datasheet.
- pin 36 is V_BCKP on /3V3 (always-on), deliberately not /3V3_GNSS:
RTC + ephemeris survive when U21's switched rail is off
- no /3V3 cap existed within 19 mm of the pin; spare Cu4 (100nF,
already /3V3-GND) reassigned to sit at pin 36
- C123 clarified: U18 has only two VCC pins; C123 is the U21-output
third 100nF, not a VCC-pin cap
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
- every discrete mapped to its owner designator with distance class
(glued <=3mm / close <=5mm / block <=15mm), computed from the live
netlist + hand curation (ESD at connectors, ADC filters at MCU,
comp caps at their regulator, DB1-4 -> U13, C106-108 -> U16 VDD)
- designators added to existing per-block tables (Leo's request)
- sch<->pcb designator audit: P1-P12 in sync, 0 value mismatches,
only expected diffs (U22 fp TBD, MH5/6 board-only, PF* ERC flags)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
03-Architecture-Hardware/kicad is now its own repository so it can live on
GitHub and be pull-mirrored to the Gitea instance (Helgen-Services/HBox_PCB
on git.helgen.online).
History was extracted with:
git subtree split --prefix=03-Architecture-Hardware/kicad
so all 70 board commits survive in the submodule, with new hashes.
Parent history is untouched; tag pre-kicad-submodule-2026-08-26 marks the
state before this change.
Leo's ERC flagged exactly two errors after the T4 sync:
1. U18 pin 2 RF_IN [Input] undriven - my hand-built ZED-F9P symbol typed the RF port as a
logic input. RF ports are conventionally passive; retyped in Drogheda-sym AND the
schematic's lib_symbols cache (1 substitution each, asserted). Its real connection
arrives with the Block S bias tee in T6.
2. U22 pin 1 VCC [Power input] undriven - SIM_VDD is fed by the modem's USIM1_VDD, whose
EasyEDA pin type is not a power output. Idiomatic fix: PF18 PWR_FLAG on SIM_VDD,
consistent with PF1-PF17.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
