Hardware v6: auditoría pre-fabricación ES/EN + guías de cobre EMC
Lista de trabajo para Michelle (U25/U20, vías térmicas, anchos de potencia, F2), pendientes de Leo y parámetros de pedido JLCPCB. Diagrama del lazo caliente de U25. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
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docs/hardware/EinarBoard-v6_Copper-Plan_EN.html
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<title>EinarBoard v6 Copper Plan</title>
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<link rel="stylesheet" href="https://fonts.googleapis.com/css2?family=Archivo:wght@500;600;700&family=IBM+Plex+Sans:ital,wght@0,400;0,500;0,600;1,400&family=IBM+Plex+Mono:wght@400;500&display=swap">
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<style>
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:root{
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--paper:#faf8f4; --ink:#1d1c19; --ink2:#5a564d; --line:#e2ddd2;
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--copper:#a4611f; --copper-soft:#f3e7d6; --plane:#33586e; --plane-soft:#e3ebf0;
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--crit:#a63b2a; --crit-soft:#f6e5e1; --ok:#43704c;
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:root:not([data-theme="light"]){ }
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:root:not([data-theme="light"]){
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--paper:#191b1e; --ink:#e3ded4; --ink2:#a09a8d; --line:#33363b;
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--copper:#d99b52; --copper-soft:#2e2519; --plane:#8fb4c9; --plane-soft:#1f2a31;
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--crit:#e08373; --crit-soft:#33211d; --ok:#8fbf98;
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--paper:#191b1e; --ink:#e3ded4; --ink2:#a09a8d; --line:#33363b;
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--copper:#d99b52; --copper-soft:#2e2519; --plane:#8fb4c9; --plane-soft:#1f2a31;
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--crit:#e08373; --crit-soft:#33211d; --ok:#8fbf98;
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--card:#1f2226; --mono-bg:#25282d;
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}
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body{background:var(--paper);color:var(--ink);font:400 15.5px/1.55 "IBM Plex Sans",system-ui,sans-serif;margin:0}
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.wrap{max-width:900px;margin:0 auto;padding:40px 22px 80px}
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h1,h2,h3{font-family:"Archivo",system-ui,sans-serif;text-wrap:balance;margin:0}
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h1{font-size:30px;font-weight:700;letter-spacing:-.01em}
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.sub{color:var(--ink2);margin:6px 0 0;max-width:64ch}
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h2{font-size:19px;font-weight:600;margin:44px 0 6px;padding-top:14px;border-top:2px solid var(--copper)}
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h2 .no{color:var(--copper);font-family:"IBM Plex Mono",monospace;font-size:14px;font-weight:500;margin-right:8px}
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h3{font-size:15.5px;font-weight:600;margin:20px 0 4px}
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p{margin:8px 0;max-width:72ch}
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code,.rf{font-family:"IBM Plex Mono",monospace;font-size:.92em;background:var(--mono-bg);padding:1px 5px;border-radius:3px;white-space:nowrap}
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.lead{font-size:16.5px}
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table{border-collapse:collapse;width:100%;margin:10px 0;font-size:14px}
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th{font-family:"Archivo",sans-serif;font-size:11.5px;text-transform:uppercase;letter-spacing:.07em;color:var(--ink2);text-align:left;padding:6px 10px 6px 0;border-bottom:1px solid var(--ink2)}
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td{padding:6px 10px 6px 0;border-bottom:1px solid var(--line);vertical-align:top}
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td:first-child{font-family:"IBM Plex Mono",monospace;font-size:13px;white-space:nowrap}
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.tblwrap{overflow-x:auto}
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.loop{background:var(--copper-soft);border-left:3px solid var(--copper);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
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.loop b:first-child{color:var(--copper)}
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.warn{background:var(--crit-soft);border-left:3px solid var(--crit);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
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.warn b:first-child{color:var(--crit)}
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.note{background:var(--plane-soft);border-left:3px solid var(--plane);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
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.laws{display:grid;grid-template-columns:repeat(auto-fit,minmax(240px,1fr));gap:12px;margin:18px 0}
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.law{background:var(--card);border:1px solid var(--line);border-radius:8px;padding:14px 16px}
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.law b{display:block;font-family:"Archivo",sans-serif;font-size:14px;margin-bottom:4px;color:var(--copper)}
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.law p{font-size:13.5px;margin:0;color:var(--ink2)}
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figure{margin:16px 0}
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figcaption{font-size:12.5px;color:var(--ink2);margin-top:6px}
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svg text{font-family:"IBM Plex Mono",monospace}
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ol.steps{counter-reset:s;list-style:none;padding:0;margin:14px 0}
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ol.steps li{counter-increment:s;padding:10px 0 10px 44px;position:relative;border-bottom:1px solid var(--line);max-width:76ch}
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ol.steps li::before{content:counter(s,decimal-leading-zero);position:absolute;left:0;top:10px;font-family:"IBM Plex Mono",monospace;color:var(--copper);font-weight:500}
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ul{padding-left:20px}
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li{margin:4px 0}
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.tag{font-family:"Archivo",sans-serif;font-size:10.5px;text-transform:uppercase;letter-spacing:.08em;padding:2px 7px;border-radius:99px;border:1px solid var(--copper);color:var(--copper);white-space:nowrap}
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.tag.q{border-color:var(--plane);color:var(--plane)}
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.d{font-family:"Archivo",sans-serif;font-size:10px;font-weight:600;letter-spacing:.05em;padding:1px 6px;border-radius:99px;white-space:nowrap}
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.d1{background:var(--crit-soft);color:var(--crit)}
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.d2{background:var(--copper-soft);color:var(--copper)}
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.d3{background:var(--plane-soft);color:var(--plane)}
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tr.own td{font-family:"Archivo",sans-serif;font-size:12.5px;font-weight:600;text-transform:uppercase;letter-spacing:.06em;color:var(--copper);border-bottom:2px solid var(--copper);padding-top:18px;white-space:normal}
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a{color:var(--plane)}
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</style>
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<div class="wrap">
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<h1>EinarBoard v6 Copper Plan</h1>
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<p class="sub">Placement companion for the 140 × 100 re-layout — every capacitor's owner, what clusters together, and the EMC order of work. Cap ownership below is computed from the board netlist, not from memory.</p>
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<div class="note"><b>Connector renumber (03-Sep, commit <code>b007c7c</code>):</b> P-refs now follow function order — <code>P1</code> 24V · <code>P2</code> 5V bench · <code>P3</code> battery (was P4) · <code>P4</code> fan (was P6) · <code>P5</code> cutoff (was P11) · <code>P6</code> reset (was P10) · <code>P7</code> NTC probe 1 (was P12) · <code>P8</code> NTC probe 2 (was P18) · <code>P9</code> panel LED (was P8) · <code>P10</code> RGB (was P14) · <code>P11</code> RS485 (was P15) · <code>P12</code> RS232 (was P16). ⚠ v5 field docs say "P12 = NTC" — in v6 that name is the RS232 port; update harness docs. The NTC2 net fix is applied and synced.</div>
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<div class="note"><b>Known leftovers from the auto-clustering:</b> ~54 small courtyard overlaps, nearly all against the legacy V5 regulator families that kept their old spots — <code>L2</code>/<code>D2</code> (under U19's new outline), <code>L6</code>/<code>DB2</code>/<code>DB3</code>/<code>Q2</code>/<code>Dbk1</code> near U25, <code>C40</code>, <code>R40</code>/<code>R41</code> at Y3. Drag those few aside first and the board is clean.</div>
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<h2><span class="no">§0</span>Three laws that decide EMC at placement time</h2>
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<div class="laws">
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<div class="law"><b>Loop area is the antenna</b><p>Emission scales with the area of each switching current loop. A hot loop closed in 1 cm² is ~20 dB quieter than the same loop at 10 cm². Placement fixes this; routing can't rescue a bad placement.</p></div>
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<div class="law"><b>Smallest cap closest</b><p>A capacitor filters up to the frequency its trace inductance allows. Order banks by descending value <i>toward</i> the pin: bulk → 10 µF → 100 nF → pF, with the pF parts within 2–3 mm.</p></div>
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<div class="law"><b>Aggressors far from victims</b><p>Four switchers, one LTE transmitter, one −167 dBm GNSS receiver on one board. Distance and an unbroken In1 ground plane are the only broadband shields you get for free.</p></div>
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</div>
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<h2><span class="no">§1</span>Floorplan as clustered (NW ETH · NE LTE · SW GNSS · SE power)</h2>
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<figure>
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<svg viewBox="0 0 700 500" style="max-width:100%;height:auto" role="img" aria-label="Current floorplan of the 140 by 100 mm board">
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<rect x="30" y="40" width="630" height="450" fill="none" stroke="var(--ink)" stroke-width="2"/>
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<text x="30" y="28" font-size="12" fill="var(--ink2)">140 × 100 mm · as clustered on 03-Sep (commit c7d2552) · N = top of the KiCad screen</text>
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<!-- NW ETH -->
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<rect x="32" y="42" width="200" height="130" fill="var(--plane-soft)"/>
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<text x="42" y="64" font-size="13" fill="var(--plane)">NW — ETHERNET</text>
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<text x="42" y="81" font-size="11" fill="var(--ink2)">J10 RJ45 · U11/U12 · Y1</text>
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<text x="42" y="96" font-size="11" fill="var(--ink2)">C90–C103 · J11 USB-DFU</text>
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<!-- NE LTE -->
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<rect x="440" y="42" width="218" height="200" fill="var(--copper-soft)"/>
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<text x="452" y="64" font-size="13" fill="var(--copper)">NE — LTE ISLAND</text>
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<text x="452" y="81" font-size="11" fill="var(--ink2)">U20 buck+L20 · VBAT bank</text>
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<text x="452" y="96" font-size="11" fill="var(--ink2)">U19 A7670SA · K1 · shifters</text>
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<text x="452" y="111" font-size="11" fill="var(--ink2)">J13 U.FL → NE corner</text>
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<!-- MCU -->
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<rect x="250" y="90" width="170" height="150" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
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<text x="335" y="115" font-size="13" text-anchor="middle" fill="var(--ink)">MCU U16</text>
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<text x="335" y="132" font-size="11" text-anchor="middle" fill="var(--ink2)">crystals · VCAP · VDDA</text>
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<text x="335" y="147" font-size="11" text-anchor="middle" fill="var(--ink2)">sense RCs · U10/Y2 below</text>
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<!-- SW GNSS -->
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<rect x="32" y="255" width="200" height="233" fill="var(--plane-soft)"/>
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<text x="42" y="277" font-size="13" fill="var(--plane)">SW — GNSS ISLAND</text>
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<text x="42" y="294" font-size="11" fill="var(--ink2)">U21 LDO · C119–C124</text>
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<text x="42" y="309" font-size="11" fill="var(--ink2)">U18 F9P · L21 bias tee</text>
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<text x="42" y="324" font-size="11" fill="var(--ink2)">C143/144/145 · D27 · J12 → W edge</text>
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<text x="42" y="345" font-size="11" fill="var(--ink2)">U26 accel at MH6 (SW hole)</text>
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<text x="42" y="366" font-size="11" fill="var(--crit)">quiet corner — no switchers</text>
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<!-- SE power -->
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<rect x="440" y="290" width="218" height="198" fill="var(--copper-soft)"/>
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<text x="452" y="312" font-size="13" fill="var(--copper)">SE — POWER ENTRY</text>
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<text x="452" y="329" font-size="11" fill="var(--ink2)">P1 24V · F2 Q23 D32 · 24V parts</text>
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<text x="452" y="344" font-size="11" fill="var(--ink2)">U25 + L22 + C149–C154</text>
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<text x="452" y="359" font-size="11" fill="var(--ink2)">U6 LTC4040 + RS1 · fan U2 above</text>
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<text x="452" y="374" font-size="11" fill="var(--ink2)">J9 USB · RS232 U15 just west</text>
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<!-- diagonal separation -->
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<line x1="235" y1="370" x2="500" y2="130" stroke="var(--crit)" stroke-dasharray="6 5"/>
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<text x="368" y="262" font-size="11" text-anchor="middle" fill="var(--crit)" transform="rotate(-42 368 262)">GNSS ↔ LTE on the diagonal · antennas ≥ 20 cm at the enclosure</text>
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</svg>
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<figcaption>The clustered state after commit <code>c7d2552</code> — your anchors kept (J10, P1, U18, U16, U6, U15, K1, connectors), 160 support parts packed by family. Fine-tune freely inside each region; keep the diagonal.</figcaption>
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</figure>
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<h2><span class="no">§2</span>Vehicle power entry — U25 TPS54360B <span class="tag">hot loop</span></h2>
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<p>Chain order along the copper, left to right from P1: <code>F2</code> → <code>Q23</code> (with <code>R119</code>, <code>D33</code> beside its gate) → <code>D32</code> SMCJ33A → input caps → <code>U25</code> → <code>D34</code>/<code>L22</code> → output caps. <code>D10</code> stays glued to P1 pin 1.</p>
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<div class="loop"><b>Loudest loop on the board:</b> C149/C150 (+) → U25 VIN ⟶ U25 SW → D34 cathode ⟶ D34 anode → C149/C150 (−). This is a non-synchronous buck, so the input loop carries the full di/dt. Put <code>C149</code>/<code>C150</code> within 2–3 mm of U25 pins 2/7, D34 directly across from them, and close the loop over solid ground. Under 1 cm² or do it again.</div>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>U25 VIN</td><td>2–3 mm from pins 2/7; the hot loop</td></tr>
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<tr><td>C151</td><td>100 µF/50 V</td><td>U25 input bulk</td><td>right behind C149/C150</td></tr>
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<tr><td>C152</td><td>100 nF</td><td>U25 BOOT</td><td>directly across pins 1–8</td></tr>
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<tr><td>C153 C154</td><td>47 µF/16 V</td><td>U25 5 V output</td><td>at L22 output; FB tap (R121) here, not at the inductor</td></tr>
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<tr><td>D34</td><td>B560C</td><td>U25 catch diode</td><td>anode ground ties straight into C149/C150 ground</td></tr>
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<tr><td>D32</td><td>SMCJ33A</td><td>U25 input surge clamp</td><td>between Q23 and the input caps, short fat ties</td></tr>
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<tr><td>R120 · R123 C155 C156 · R121 R122 · R124 R125</td><td>RT · COMP · FB · UVLO (DNP)</td><td>U25 analog side</td><td>cluster at pins 3–6, opposite the SW node; keep FB thin and away from L22</td></tr>
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</table></div>
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<p>24 V rail housekeeping: <code>C10</code>/<code>C22</code> bulk near Q10, <code>C11</code> 100 nF at the load side. Keep the whole entry block in one corner so the dirty 24 V copper never crosses the board.</p>
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<h2><span class="no">§3</span>Battery backup — U6 LTC4040 <span class="tag q">kelvin</span></h2>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>U6 VEH5V input</td><td>at U6 input pins, after RS1</td></tr>
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<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>U6 MAIN5V output</td><td>at U6/Q7 output side</td></tr>
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<tr><td>C35</td><td>22 µF</td><td>U6 BAT pin → P3</td><td>near P3; <code>/SW_BAT</code> ≥ 2 mm polygon, <code>/BAT_PLUS</code> ≥ 1.5 mm — the blackout path, a hard v6 requirement</td></tr>
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</table></div>
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<div class="note"><b>RS1 (10 mΩ) is a Kelvin part:</b> the LTC4040 sense pins must tap the pad faces themselves, not the power trace. Place RS1 immediately at U6 with L22's output feeding it directly.</div>
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<h2><span class="no">§4</span>LTE island — U20 buck + U19 A7670SA <span class="tag">hot loop</span></h2>
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<div class="loop"><b>Second hot loop:</b> C127/C128 → U20 VIN/GND. Synchronous buck, so the input loop is the loud one — C127 10 µF within 2–3 mm of U20 pin 2, C128 1 µF even closer. C129 boot across BOOT–SW, L20 right at SW with a minimal SW pour.</div>
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<p>The VBAT bank is a one-direction gradient into pins 55/56/57 — largest farthest, smallest touching the module:</p>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Order</th><th>Placement</th></tr>
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<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>U19 VBAT · far end</td><td>the ≥300 µF droop reservoir (2.8 A bursts, ≤300 mV sag)</td></tr>
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<tr><td>C132 → C133 → C134</td><td>22 µF → 1 µF → 100 nF</td><td>U19 VBAT · middle</td><td>stepping toward the module</td></tr>
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<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>U19 pins 55/56/57</td><td>within 2–3 mm — these keep TX harmonics off VBAT</td></tr>
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<tr><td>D22</td><td>SMAJ5.0A</td><td>U19 VBAT bank</td><td>across VBAT near C130/C131</td></tr>
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</table></div>
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<p>VBAT copper ≥ 3 mm wide the whole way. Around the module: <code>C125</code> at pin 15 (1V8 out); <code>U22</code> SIM within 5 mm of pins 30–33 with <code>C126</code> at its VCC pad and <code>D23–D25</code> PESD at the SIM pads; <code>U23</code>/<code>U24</code> level shifters between U19 and the MCU side, each with its supply pair (<code>C137</code>/<code>C139</code> on 1V8, <code>C138</code>/<code>C140</code> on 3V3) at the pins; <code>Q20–Q22</code> near the control pins they drive. <code>J13</code> U.FL at the board edge; the DNP pi network <code>C146</code>/<code>C147</code> (+ its series element) sits inline in the 50 Ω run right at the connector, <code>D28</code> ESD at the connector ground side.</p>
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<h2><span class="no">§5</span>GNSS island — U18 ZED-F9P + U21 LDO <span class="tag q">quiet</span></h2>
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<div class="tblwrap"><table>
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<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
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<tr><td>C119</td><td>10 µF</td><td>U21 input (SW_5V)</td><td>at the LDO input pin</td></tr>
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||||||
|
<tr><td>C120 C124</td><td>10 µF ×2</td><td>U21 out → U18 VCC</td><td>one at U21 output, one at U18's main VCC entry</td></tr>
|
||||||
|
<tr><td>C121 C122</td><td>100 nF ×2</td><td>U18 VCC pins 33/34</td><td>one per supply pin, at the pin</td></tr>
|
||||||
|
<tr><td>C123</td><td>100 nF</td><td>U21 VOUT, beside C120</td><td>U18 has only two VCC pins — C123 is the rail-entry third</td></tr>
|
||||||
|
<tr><td>Cu4</td><td>100 nF</td><td>U18 pin 36 V_BCKP (/3V3!)</td><td>V_BCKP rides the always-on 3V3, not 3V3_GNSS — that is deliberate (RTC + ephemeris survive when U21 is switched off). It needs its own /3V3 cap at the pin; C120–C124 are all on /3V3_GNSS and cannot serve it. Repurpose the spare Cu4.</td></tr>
|
||||||
|
<tr><td>C144 C145</td><td>100 nF · 100 pF</td><td>U18 VCC_RF · L21 bias tee</td><td>at L21's feed side — the antenna supply injection</td></tr>
|
||||||
|
<tr><td>C143</td><td>100 nF RF</td><td>J12 RF line (DC block)</td><td>inline in the 50 Ω run between L21 tap and J12</td></tr>
|
||||||
|
<tr><td>D27</td><td>ESD9L (≤0.5 pF)</td><td>J12</td><td>at the connector, stub-less tap on the RF line</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<p>This corner is the victim: no switcher, no inductor, no fast digital within ~25 mm (U25 sits ~95 mm away in the SE, the fan buck ~130 mm NE — keep it that way); nothing but solid In1 ground under the module and the RF run. <code>TIMEPULSE</code> to the MCU is the one digital line that leaves — route it away from the RF path.</p>
|
||||||
|
|
||||||
|
<h2><span class="no">§6</span>MCU core — U16 <span class="tag q">analog care</span></h2>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Value</th><th>Belongs to</th><th>Placement</th></tr>
|
||||||
|
<tr><td>C111</td><td>4.7 µF</td><td>U16 VCAP1</td><td>≤ 3 mm from the pin — the core regulator, non-negotiable</td></tr>
|
||||||
|
<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>U16 VDDA</td><td>at the VDDA pin, on the quiet side, away from the switchers</td></tr>
|
||||||
|
<tr><td>C105–C108 + C110</td><td>100 nF ×4 + 4.7 µF</td><td>U16 VDD pins</td><td>one 100 nF per VDD pin, bulk nearby</td></tr>
|
||||||
|
<tr><td>C104</td><td>100 nF</td><td>U16 NRST</td><td>at the pin, with the P6 reset jack routed clean</td></tr>
|
||||||
|
<tr><td>Y3 + C113 C114</td><td>HSE + 15 pF</td><td>U16 OSC pins</td><td>tight triangle at the pins, local ground, ≥10 mm from any inductor</td></tr>
|
||||||
|
<tr><td>Y4 + C115 C116</td><td>LSE 32 kHz + 12 pF</td><td>U16 OSC32 pins</td><td>even tighter — high-impedance oscillator, guard with ground</td></tr>
|
||||||
|
<tr><td>C5 C7 C9 C24 C157</td><td>100 nF ×5</td><td>U16 ADC pins</td><td>with their dividers (R42, R126…) at the MCU pins, not at the jacks — the wire filters at the pin</td></tr>
|
||||||
|
</table></div>
|
||||||
|
|
||||||
|
<h2><span class="no">§7</span>The rest of the families</h2>
|
||||||
|
<ul>
|
||||||
|
<li><b>Ethernet</b> (<code>U11</code>/<code>U12</code>, <code>Y1</code>, <code>C90–C103</code>): one block, U11 close to J10 (magnetics are inside the HR911105A), crystal + 18 pF at the pins, the 3V3_ETH locals (<code>C92–C94</code>, <code>C98</code>, <code>C102</code>, <code>C103</code>) around U11. Keep the RJ45 pair region free of other routes.</li>
|
||||||
|
<li><b>RS232</b> (<code>U15</code>): <code>C85–C88</code> are charge-pump flying caps — they carry the pump current, so they sit hard against U15; <code>C84</code> 100 nF at its supply pin. P12 (RS232 jack) at the edge.</li>
|
||||||
|
<li><b>UART bridge</b> (<code>U10</code>, <code>Y2</code>, <code>C82</code>/<code>C83</code>): crystal caps at the pins, block near the MCU.</li>
|
||||||
|
<li><b>Fan buck</b> (<code>U2</code>, <code>Cbst1</code>, <code>Ccomp1</code>, <code>C23</code>): a third switcher — treat like §4's loop, and park it in the noisy quarter near the power entry, away from GNSS.</li>
|
||||||
|
<li><b>Accelerometer</b> (<code>U26</code>, <code>C158</code>/<code>C159</code> at VDD/VDDIO, <code>C160</code> bulk): ≤ 10 mm from a mounting hole, on stiff board — it should feel the chassis, not board flex.</li>
|
||||||
|
<li><b>Rail sprinkles</b> (<code>Cu3</code> <code>Cu4</code> <code>C80</code> <code>C81</code> <code>C89</code> <code>C105+</code>…): every 100 nF on 3V3 pairs with one IC's power pin — when you move an IC, its 100 nF moves with it. <code>C118</code> 22 µF is the 3V3 bulk at the regulator.</li>
|
||||||
|
<li><b>NTC channels</b>: pullup + filter (<code>R42</code>+<code>C24</code> → P7, <code>R126</code>+<code>C157</code> → P8) at the MCU; <code>P7</code>/<code>P8</code> jacks at the harness edge.</li>
|
||||||
|
</ul>
|
||||||
|
|
||||||
|
<h2><span class="no">§8</span>Master proximity table — every discrete, its owner designator, and how close</h2>
|
||||||
|
<p>Computed from the current board netlist (post-rename, all 300 footprints), then hand-corrected where the netlist heuristic picked a connected-but-wrong owner (ESD parts belong at connectors, ADC filters at the MCU, comp caps at their regulator). Distance classes:</p>
|
||||||
|
<p><span class="d d1">🔴 GLUED ≤3 mm</span> loop-critical — same pad ground, no via between <span class="d d2">🟠 CLOSE ≤5 mm</span> at the pin, short direct trace <span class="d d3">🔵 BLOCK ≤15 mm</span> same cluster, routing order free</p>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Value</th><th>Glue to</th><th></th><th>Why</th></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">P1 — 24 V entry (SE corner)</td></tr>
|
||||||
|
<tr><td>D10</td><td>SMBJ33A</td><td>P1 pin 1 (24V_IN)</td><td><span class="d d1">🔴</span></td><td>surge clamp at the jack, before anything else</td></tr>
|
||||||
|
<tr><td>Rig1</td><td>22k</td><td>P1 ignition pin</td><td><span class="d d1">🔴</span></td><td>series element right at the jack</td></tr>
|
||||||
|
<tr><td>F2</td><td>2 A slow 1812</td><td>P1 → Q23</td><td><span class="d d3">🔵</span></td><td>first element in the chain</td></tr>
|
||||||
|
<tr><td>Q23</td><td>IRFR5305</td><td>F2 output</td><td><span class="d d3">🔵</span></td><td>reverse-polarity FET, chain order</td></tr>
|
||||||
|
<tr><td>R119 D33</td><td>100k · BZX84C15</td><td>Q23 G–S pads</td><td><span class="d d1">🔴</span></td><td>gate bias + 15 V clamp across the FET itself</td></tr>
|
||||||
|
<tr><td>D32</td><td>SMCJ33A</td><td>between Q23 and C149/C150</td><td><span class="d d2">🟠</span></td><td>clamps the line before the buck sees it</td></tr>
|
||||||
|
<tr><td>Q10</td><td>IRFR5305</td><td>P1 24 V branch</td><td><span class="d d3">🔵</span></td><td>legacy 24 V rail FET (feeds U2 + K1)</td></tr>
|
||||||
|
<tr><td>Rrp1 DzG1</td><td>10k · BZX84C15</td><td>Q10 G–S pads</td><td><span class="d d1">🔴</span></td><td>gate network — the part behind the v5.5 jumper check</td></tr>
|
||||||
|
<tr><td>C10 C22</td><td>47 µF/50 V · 22 µF/50 V</td><td>Q10 load side (/24V)</td><td><span class="d d3">🔵</span></td><td>24 V rail bulk</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U25 — TPS54360B vehicle buck</td></tr>
|
||||||
|
<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>U25 pins 2/7 (VIN–GND)</td><td><span class="d d1">🔴</span></td><td>THE hot loop of the board</td></tr>
|
||||||
|
<tr><td>D34</td><td>B560C</td><td>U25 SW + C149 ground</td><td><span class="d d1">🔴</span></td><td>closes the hot loop</td></tr>
|
||||||
|
<tr><td>C151</td><td>100 µF/50 V</td><td>behind C149/C150</td><td><span class="d d2">🟠</span></td><td>input bulk</td></tr>
|
||||||
|
<tr><td>C152</td><td>100 nF</td><td>U25 BOOT (pins 1–8)</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
|
||||||
|
<tr><td>L22</td><td>10 µH SRP1265A</td><td>U25 SW pin</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
|
||||||
|
<tr><td>C153 C154</td><td>47 µF/16 V</td><td>L22 output pad</td><td><span class="d d2">🟠</span></td><td>VEH5V output caps; FB taps here</td></tr>
|
||||||
|
<tr><td>R121 R122</td><td>53.6k · 10.2k</td><td>U25 FB pin, tap at C153</td><td><span class="d d2">🟠</span></td><td>thin trace, away from L22's field</td></tr>
|
||||||
|
<tr><td>R123 C155 C156</td><td>13k · 6.8 nF · 39 pF</td><td>U25 COMP pin</td><td><span class="d d2">🟠</span></td><td>compensation — quiet side, short ground</td></tr>
|
||||||
|
<tr><td>R120</td><td>162k</td><td>U25 RT pin</td><td><span class="d d2">🟠</span></td><td>frequency-set, short ground</td></tr>
|
||||||
|
<tr><td>R124 R125</td><td>UVLO (DNP)</td><td>U25 EN pin</td><td><span class="d d2">🟠</span></td><td>divider lands here if fitted</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U6 — LTC4040 battery backup (+P3)</td></tr>
|
||||||
|
<tr><td>RS1</td><td>10 mΩ 1%</td><td>U6 sense pins</td><td><span class="d d1">🔴</span></td><td>Kelvin — sense routes from the pad faces</td></tr>
|
||||||
|
<tr><td>L6</td><td>2.2 µH/8 A</td><td>U6 SW pins</td><td><span class="d d1">🔴</span></td><td>charger/boost loop tight</td></tr>
|
||||||
|
<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>U6 VIN, after RS1</td><td><span class="d d2">🟠</span></td><td>VEH5V bank at the input pins</td></tr>
|
||||||
|
<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>U6 MAIN5V output / Q7</td><td><span class="d d2">🟠</span></td><td>output bank</td></tr>
|
||||||
|
<tr><td>C35</td><td>22 µF</td><td>U6 BAT pin → P3</td><td><span class="d d2">🟠</span></td><td>on the wide /BAT_PLUS copper</td></tr>
|
||||||
|
<tr><td>Q7</td><td>AO4406A</td><td>U6 gate/PowerPath side</td><td><span class="d d2">🟠</span></td><td>the blackout switch</td></tr>
|
||||||
|
<tr><td>R50</td><td>825R 1%</td><td>U6 PROG pin</td><td><span class="d d1">🔴</span></td><td>precision current-program R</td></tr>
|
||||||
|
<tr><td>R51 R52</td><td>270k · 100k</td><td>U6 PFI pin</td><td><span class="d d2">🟠</span></td><td>power-fail divider</td></tr>
|
||||||
|
<tr><td>R53 R54</td><td>499k · 100k</td><td>U6 FB pin</td><td><span class="d d2">🟠</span></td><td>boost feedback</td></tr>
|
||||||
|
<tr><td>R55</td><td>10k 1%</td><td>U6 NTC pin</td><td><span class="d d2">🟠</span></td><td>pack-thermistor divider (probe enters at P3)</td></tr>
|
||||||
|
<tr><td>JP2 JP3 JP4</td><td>F-straps</td><td>U6 F0/F1/F2 pins</td><td><span class="d d3">🔵</span></td><td>logic straps</td></tr>
|
||||||
|
<tr><td>R56 R57 R58</td><td>100k ×3</td><td>U6 ↔ U16 route</td><td><span class="d d3">🔵</span></td><td>status/enable pulls, anywhere on the line</td></tr>
|
||||||
|
<tr><td>TP1 TP2</td><td>CLPROG · PFO</td><td>U6 block edge</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U2 — MP1584 fan buck (+P4)</td></tr>
|
||||||
|
<tr><td>C11</td><td>100 nF</td><td>U2 VIN pin</td><td><span class="d d1">🔴</span></td><td>non-sync input loop (C10/C22 bulk behind)</td></tr>
|
||||||
|
<tr><td>Dbk1</td><td>SS34</td><td>U2 SW + input ground</td><td><span class="d d1">🔴</span></td><td>catch diode — same loop</td></tr>
|
||||||
|
<tr><td>Cbst1</td><td>10 nF</td><td>U2 BOOT–SW</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
|
||||||
|
<tr><td>L2</td><td>10 µH</td><td>U2 SW</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
|
||||||
|
<tr><td>C23</td><td>22 µF/16 V</td><td>L2 output → P4</td><td><span class="d d2">🟠</span></td><td>5V_FAN output cap</td></tr>
|
||||||
|
<tr><td>R20 R21</td><td>100k · 19.1k</td><td>U2 FB, tap at C23</td><td><span class="d d2">🟠</span></td><td>feedback divider</td></tr>
|
||||||
|
<tr><td>Rcomp1 Ccomp1</td><td>40.2k · 2.2 nF</td><td>U2 COMP pin</td><td><span class="d d2">🟠</span></td><td>compensation</td></tr>
|
||||||
|
<tr><td>Rfreq1</td><td>100k</td><td>U2 FREQ pin</td><td><span class="d d2">🟠</span></td><td>frequency-set</td></tr>
|
||||||
|
<tr><td>Ren1 Ren2</td><td>100k · 20k</td><td>U2 EN pin</td><td><span class="d d3">🔵</span></td><td>enable divider</td></tr>
|
||||||
|
<tr><td>D2</td><td>SS34</td><td>P4 pins</td><td><span class="d d1">🔴</span></td><td>flyback right at the fan jack</td></tr>
|
||||||
|
<tr><td>Q2 Rgs1</td><td>AO3400A · 100k</td><td>P4 return · Rgs1 on Q2 G–S</td><td><span class="d d2">🟠</span></td><td>low-side switch at the jack, G–S resistor glued</td></tr>
|
||||||
|
<tr><td>Q5 Rg1</td><td>MMBT3904 · 100R</td><td>Q2 gate</td><td><span class="d d3">🔵</span></td><td>gate driver stage</td></tr>
|
||||||
|
<tr><td>JP1</td><td>0R</td><td>P4 5V_FAN link</td><td><span class="d d3">🔵</span></td><td>current-measure link</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U20 — AP64350 modem buck</td></tr>
|
||||||
|
<tr><td>C127 C128</td><td>10 µF · 1 µF</td><td>U20 VIN pin 2</td><td><span class="d d1">🔴</span></td><td>sync input loop — 1 µF closest of all</td></tr>
|
||||||
|
<tr><td>C129</td><td>100 nF</td><td>U20 BOOT–SW</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
|
||||||
|
<tr><td>L20</td><td>4.7 µH/5 A</td><td>U20 SW</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
|
||||||
|
<tr><td>D21</td><td>PMEG3050EP</td><td>U20 VIN feed</td><td><span class="d d2">🟠</span></td><td>input ORing</td></tr>
|
||||||
|
<tr><td>D20</td><td>SS34</td><td>24 V → U20 input branch</td><td><span class="d d3">🔵</span></td><td>feed diode</td></tr>
|
||||||
|
<tr><td>R110 R111</td><td>75k · 20k</td><td>U20 FB pin</td><td><span class="d d2">🟠</span></td><td>feedback divider</td></tr>
|
||||||
|
<tr><td>R116 C141 C142</td><td>14k · 3.3 nF · 47 pF</td><td>U20 COMP pin</td><td><span class="d d2">🟠</span></td><td>compensation</td></tr>
|
||||||
|
<tr><td>R117</td><td>200k 1%</td><td>U20 RT pin</td><td><span class="d d2">🟠</span></td><td>frequency-set</td></tr>
|
||||||
|
<tr><td>R113</td><td>100k</td><td>U20 EN pin</td><td><span class="d d3">🔵</span></td><td>enable pull</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U19 — A7670SA modem (+U22 SIM · U23/U24 · K1 · J13)</td></tr>
|
||||||
|
<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>U19 pins 55/56/57</td><td><span class="d d1">🔴</span></td><td>TX-harmonic filters — the closest of the bank</td></tr>
|
||||||
|
<tr><td>C134 C133 C132</td><td>100 nF → 1 µF → 22 µF</td><td>stepping back from those pins</td><td><span class="d d2">🟠</span></td><td>the gradient</td></tr>
|
||||||
|
<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>far end of U19's VBAT bank</td><td><span class="d d3">🔵</span></td><td>≥300 µF burst reservoir</td></tr>
|
||||||
|
<tr><td>D22</td><td>SMAJ5.0A</td><td>at C130/C131</td><td><span class="d d2">🟠</span></td><td>VBAT clamp</td></tr>
|
||||||
|
<tr><td>R112</td><td>1k</td><td>U19 VBAT side</td><td><span class="d d3">🔵</span></td><td>bleed/monitor</td></tr>
|
||||||
|
<tr><td>C125</td><td>2.2 µF</td><td>U19 pin 15 (1V8 out)</td><td><span class="d d1">🔴</span></td><td>LDO output cap</td></tr>
|
||||||
|
<tr><td>U22</td><td>SIM (fp TBD)</td><td>U19 pins 30–33, ≤5 mm</td><td><span class="d d2">🟠</span></td><td>unshielded SIM bus</td></tr>
|
||||||
|
<tr><td>C126</td><td>100 nF</td><td>U22 VCC pad</td><td><span class="d d1">🔴</span></td><td>SIM supply</td></tr>
|
||||||
|
<tr><td>D23 D24 D25</td><td>PESD5V0S1BA</td><td>U22 SIM pads</td><td><span class="d d1">🔴</span></td><td>ESD at the socket, not mid-route</td></tr>
|
||||||
|
<tr><td>U23 U24</td><td>74LVC2T45</td><td>between U19 and U16</td><td><span class="d d3">🔵</span></td><td>level shifters sit on the path</td></tr>
|
||||||
|
<tr><td>C137 C139</td><td>100 nF</td><td>U23/U24 1V8 pins</td><td><span class="d d1">🔴</span></td><td>supply pair, one each</td></tr>
|
||||||
|
<tr><td>C138 C140</td><td>100 nF</td><td>U23/U24 3V3 pins</td><td><span class="d d1">🔴</span></td><td>supply pair, one each</td></tr>
|
||||||
|
<tr><td>Q20 R114</td><td>2N7002 · 100k</td><td>U19 PWRKEY side</td><td><span class="d d3">🔵</span></td><td>open-drain driver</td></tr>
|
||||||
|
<tr><td>Q21 R115</td><td>2N7002 · 100k</td><td>U19 RESET side</td><td><span class="d d3">🔵</span></td><td>open-drain driver</td></tr>
|
||||||
|
<tr><td>R109 Q22 Rmled1 D4G1</td><td>NETLIGHT chain</td><td>U19 netlight pin → LED at a visible spot</td><td><span class="d d3">🔵</span></td><td>status LED driver</td></tr>
|
||||||
|
<tr><td>R106 R107 R108</td><td>100R · 0R ×2</td><td>U23/U24 line ends</td><td><span class="d d3">🔵</span></td><td>UART series elements</td></tr>
|
||||||
|
<tr><td>TP8</td><td>USB_BOOT</td><td>U19 BOOT pin</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
|
||||||
|
<tr><td>R118 C146 C147</td><td>0R · DNP pi</td><td>inline in the 50 Ω run, U19 RF pad → J13</td><td><span class="d d1">🔴</span></td><td>matching seats — zero stubs</td></tr>
|
||||||
|
<tr><td>D28</td><td>ESD9L</td><td>J13</td><td><span class="d d1">🔴</span></td><td>at the connector, stub-less</td></tr>
|
||||||
|
<tr><td>D6</td><td>1N4148W</td><td>K1 coil pins</td><td><span class="d d1">🔴</span></td><td>flyback across the coil</td></tr>
|
||||||
|
<tr><td>Q6 R2 C101</td><td>MMBT3904 · 10k · 22 µF</td><td>K1 coil side</td><td><span class="d d2">🟠</span></td><td>relay driver + coil supply cap</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U18 — ZED-F9P GNSS (+U21 LDO · J12)</td></tr>
|
||||||
|
<tr><td>C121 C122</td><td>100 nF ×2</td><td>U18 VCC pins 33/34, one each</td><td><span class="d d1">🔴</span></td><td>per-pin decouplers</td></tr>
|
||||||
|
<tr><td>C123</td><td>100 nF</td><td>U21 VOUT beside C120</td><td><span class="d d2">🟠</span></td><td>third 100 nF — rail entry, not a third VCC pin</td></tr>
|
||||||
|
<tr><td>Cu4</td><td>100 nF</td><td>U18 pin 36 V_BCKP — on /3V3</td><td><span class="d d1">🔴</span></td><td>only /3V3 cap in the corner; backup rail stays alive when U21 is off</td></tr>
|
||||||
|
<tr><td>C120 C124</td><td>10 µF ×2</td><td>U21 output · U18 VCC entry</td><td><span class="d d1">🔴</span></td><td>LDO stability + local bulk</td></tr>
|
||||||
|
<tr><td>C119</td><td>10 µF</td><td>U21 input pin</td><td><span class="d d1">🔴</span></td><td>LDO input</td></tr>
|
||||||
|
<tr><td>C3 C40</td><td>47 µF · 22 µF</td><td>SW_5V feed near U21</td><td><span class="d d2">🟠</span></td><td>upstream bulk</td></tr>
|
||||||
|
<tr><td>Q1</td><td>AO3401A</td><td>upstream of U21 on SW_5V</td><td><span class="d d3">🔵</span></td><td>rail switch</td></tr>
|
||||||
|
<tr><td>R105</td><td>10k</td><td>U18 pull-up</td><td><span class="d d3">🔵</span></td><td>strap</td></tr>
|
||||||
|
<tr><td>L21 C144 C145</td><td>68 nH · 100 nF · 100 pF</td><td>bias-tee tap on the 50 Ω run</td><td><span class="d d1">🔴</span></td><td>antenna supply injection</td></tr>
|
||||||
|
<tr><td>C143</td><td>100 nF RF</td><td>inline, L21 tap → J12</td><td><span class="d d1">🔴</span></td><td>DC block</td></tr>
|
||||||
|
<tr><td>D27</td><td>ESD9L ≤0.5 pF</td><td>J12</td><td><span class="d d1">🔴</span></td><td>at the connector, stub-less</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U16 — STM32 MCU (+Y3/Y4 · J11/J9 USB · sense jacks)</td></tr>
|
||||||
|
<tr><td>C111</td><td>4.7 µF</td><td>U16 VCAP1 pin</td><td><span class="d d1">🔴</span></td><td>core regulator — non-negotiable</td></tr>
|
||||||
|
<tr><td>R104</td><td>10R</td><td>U16 VDDA feed</td><td><span class="d d1">🔴</span></td><td>analog supply filter element</td></tr>
|
||||||
|
<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>U16 VDDA pin, behind R104</td><td><span class="d d1">🔴</span></td><td>analog decoupling</td></tr>
|
||||||
|
<tr><td>C105 C106 C107 C108</td><td>100 nF ×4</td><td>one per U16 VDD pin</td><td><span class="d d1">🔴</span></td><td>the netlist pass parked C106–C108 near U3 — they are U16's, bring them back</td></tr>
|
||||||
|
<tr><td>C110</td><td>4.7 µF</td><td>U16 VDD bulk</td><td><span class="d d2">🟠</span></td><td>local reservoir</td></tr>
|
||||||
|
<tr><td>C104</td><td>100 nF</td><td>U16 NRST pin</td><td><span class="d d1">🔴</span></td><td>the P6 jack just routes to it</td></tr>
|
||||||
|
<tr><td>Y3 C113 C114</td><td>25 MHz · 15 pF</td><td>U16 OSC pins</td><td><span class="d d1">🔴</span></td><td>tight triangle, local ground</td></tr>
|
||||||
|
<tr><td>Y4 C115 C116</td><td>32.768 kHz · 12 pF</td><td>U16 OSC32 pins</td><td><span class="d d1">🔴</span></td><td>tighter still — high-impedance osc</td></tr>
|
||||||
|
<tr><td>R5 R6 C5</td><td>10k ×2 · 100 nF</td><td>U16 BAT_SENSE ADC pin</td><td><span class="d d2">🟠</span></td><td>divider + filter at the pin</td></tr>
|
||||||
|
<tr><td>R7 R8 C7</td><td>10k ×2 · 100 nF</td><td>U16 5V_SENSE ADC pin</td><td><span class="d d2">🟠</span></td><td>divider + filter at the pin</td></tr>
|
||||||
|
<tr><td>Rig2 Rigb1 C9 D5</td><td>22k · 3.3k · 100 nF · BAT54</td><td>U16 IGN_SENSE ADC pin</td><td><span class="d d2">🟠</span></td><td>divider + filter + clamp at the pin</td></tr>
|
||||||
|
<tr><td>R42 C24</td><td>10k 1% · 100 nF</td><td>U16 NTC1 ADC pin — P7 is just the jack</td><td><span class="d d2">🟠</span></td><td>the probe wire filters at the pin</td></tr>
|
||||||
|
<tr><td>R126 C157</td><td>10k 1% · 100 nF</td><td>U16 NTC2 ADC pin (PC4) — P8 is just the jack</td><td><span class="d d2">🟠</span></td><td>same rule</td></tr>
|
||||||
|
<tr><td>R98 R99</td><td>10k ×2</td><td>U16 BOOT straps</td><td><span class="d d3">🔵</span></td><td>anywhere in the block</td></tr>
|
||||||
|
<tr><td>Rdfu1</td><td>22k</td><td>U16 USART1_RX</td><td><span class="d d3">🔵</span></td><td>series element</td></tr>
|
||||||
|
<tr><td>TP3 TP4 TP5</td><td>SWDIO · SWCLK · NRST</td><td>U16 side / P6 side</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
|
||||||
|
<tr><td>R1 R40 R56</td><td>1k · 1k · 100k</td><td>control lines U16 → power blocks</td><td><span class="d d3">🔵</span></td><td>anywhere along the route</td></tr>
|
||||||
|
<tr><td>D17</td><td>LED (blue)</td><td>U16 PC13 vicinity, visible</td><td><span class="d d3">🔵</span></td><td>heartbeat LED</td></tr>
|
||||||
|
<tr><td>Q4 Rled1</td><td>AO3400A · 10k</td><td>near the P9/P10 edge</td><td><span class="d d3">🔵</span></td><td>external-LED driver</td></tr>
|
||||||
|
<tr><td>D13</td><td>SS34</td><td>J11 VBUS</td><td><span class="d d2">🟠</span></td><td>VBUS ORing</td></tr>
|
||||||
|
<tr><td>D14 D15 D16</td><td>PESD5V0S1BA</td><td>J11 pads (DP/DM/VBUS)</td><td><span class="d d1">🔴</span></td><td>ESD at the jack — never mid-route</td></tr>
|
||||||
|
<tr><td>R100 R101</td><td>5.1k</td><td>J11 CC pads</td><td><span class="d d1">🔴</span></td><td>USB-C sink ID</td></tr>
|
||||||
|
<tr><td>Rcc1 Rcc2</td><td>5.1k</td><td>J9 CC pads</td><td><span class="d d1">🔴</span></td><td>USB-C sink ID</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U11 — W5500 Ethernet (+U12 buck · Y1 · J10)</td></tr>
|
||||||
|
<tr><td>C90</td><td>10 µF</td><td>U11 TOCAP pin</td><td><span class="d d1">🔴</span></td><td>internal-regulator cap</td></tr>
|
||||||
|
<tr><td>C91</td><td>4.7 µF</td><td>U11 1V2 pin</td><td><span class="d d1">🔴</span></td><td>core rail</td></tr>
|
||||||
|
<tr><td>C92 C93 C98</td><td>100 nF ×3</td><td>U11 VCC pins, one each</td><td><span class="d d1">🔴</span></td><td>per-pin decouplers</td></tr>
|
||||||
|
<tr><td>C94 C102</td><td>10 µF · 22 µF</td><td>U11 supply entry</td><td><span class="d d2">🟠</span></td><td>local bulk</td></tr>
|
||||||
|
<tr><td>Y1 C95 C96</td><td>25 MHz · 18 pF</td><td>U11 XI/XO pins</td><td><span class="d d1">🔴</span></td><td>tight triangle</td></tr>
|
||||||
|
<tr><td>R83</td><td>12.4k 1%</td><td>U11 RSET pin</td><td><span class="d d1">🔴</span></td><td>precision bias — short, clean ground</td></tr>
|
||||||
|
<tr><td>R84</td><td>10k</td><td>U11 PMODE</td><td><span class="d d3">🔵</span></td><td>strap</td></tr>
|
||||||
|
<tr><td>R92 R93</td><td>49.9R 1%</td><td>U11 TX pins → J10</td><td><span class="d d1">🔴</span></td><td>line terminations</td></tr>
|
||||||
|
<tr><td>R94 R95 C97</td><td>49.9R ×2 · 6.8 nF</td><td>J10 center taps</td><td><span class="d d1">🔴</span></td><td>Bob Smith / RCT network at the magjack</td></tr>
|
||||||
|
<tr><td>C103</td><td>100 µF/6.3 V</td><td>J10 3V3 feed</td><td><span class="d d2">🟠</span></td><td>magnetics supply bulk</td></tr>
|
||||||
|
<tr><td>R96 R97</td><td>330R</td><td>J10 LED pins</td><td><span class="d d3">🔵</span></td><td>link/act LEDs</td></tr>
|
||||||
|
<tr><td>D11</td><td>SS34</td><td>U12 SW + input ground</td><td><span class="d d1">🔴</span></td><td>ETH buck catch diode</td></tr>
|
||||||
|
<tr><td>C100</td><td>10 nF</td><td>U12 BOOT</td><td><span class="d d1">🔴</span></td><td>boot flyer</td></tr>
|
||||||
|
<tr><td>L8</td><td>10 µH/2 A</td><td>U12 SW</td><td><span class="d d2">🟠</span></td><td>minimal SW copper</td></tr>
|
||||||
|
<tr><td>R85 R86 R87 R88</td><td>FREQ · COMP · FB</td><td>U12 pins</td><td><span class="d d2">🟠</span></td><td>housekeeping at the IC</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U17 — AMS1117 3V3 LDO</td></tr>
|
||||||
|
<tr><td>C117</td><td>10 µF</td><td>U17 IN pin</td><td><span class="d d1">🔴</span></td><td>LDO input</td></tr>
|
||||||
|
<tr><td>C118</td><td>22 µF/16 V</td><td>U17 OUT pin</td><td><span class="d d1">🔴</span></td><td>LDO output / 3V3 bulk</td></tr>
|
||||||
|
<tr><td>D12</td><td>SS34</td><td>U17 input feed</td><td><span class="d d2">🟠</span></td><td>feed ORing</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">Serial block — U15 RS232 · U10 UART · U14 RS485 · U13 expander</td></tr>
|
||||||
|
<tr><td>C85 C86 C87 C88</td><td>100 nF ×4</td><td>U15 pump pins, hard against the IC</td><td><span class="d d1">🔴</span></td><td>flying caps carry the pump current</td></tr>
|
||||||
|
<tr><td>C84</td><td>100 nF</td><td>U15 VCC pin</td><td><span class="d d1">🔴</span></td><td>supply</td></tr>
|
||||||
|
<tr><td>Y2 C82 C83</td><td>1.8432 MHz · 22 pF</td><td>U10 XTAL pins</td><td><span class="d d1">🔴</span></td><td>tight triangle</td></tr>
|
||||||
|
<tr><td>R30 R31</td><td>4.7k</td><td>U10 side of the I2C bus</td><td><span class="d d3">🔵</span></td><td>bus pull-ups</td></tr>
|
||||||
|
<tr><td>R80 R81</td><td>10k</td><td>U10 RST/IRQ</td><td><span class="d d3">🔵</span></td><td>pulls</td></tr>
|
||||||
|
<tr><td>C81 C89</td><td>100 nF ×2</td><td>U14 VCC (one is spare)</td><td><span class="d d1">🔴</span></td><td>supply</td></tr>
|
||||||
|
<tr><td>R82 JP5</td><td>120R · strap</td><td>P11 RS485 jack</td><td><span class="d d2">🟠</span></td><td>termination lives at the connector</td></tr>
|
||||||
|
<tr><td>C80</td><td>100 nF</td><td>U13 VCC pin</td><td><span class="d d1">🔴</span></td><td>supply</td></tr>
|
||||||
|
<tr><td>RB1 RB2 RB3 RB4<br>DB1 DB2 DB3 DB4</td><td>120R + LED ×4</td><td>U13 outputs → LEDs at the visible edge</td><td><span class="d d3">🔵</span></td><td>the netlist pass parked DB1–DB4 at U25 — they belong with U13</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U26 — SC7A20 accelerometer (at MH6)</td></tr>
|
||||||
|
<tr><td>C158 C159</td><td>100 nF ×2</td><td>U26 VDD/VDDIO pins</td><td><span class="d d1">🔴</span></td><td>one per supply pin</td></tr>
|
||||||
|
<tr><td>C160</td><td>10 µF</td><td>U26 bulk</td><td><span class="d d2">🟠</span></td><td>local reservoir; U26 itself ≤10 mm from MH6</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">Panel · sensors · leftovers</td></tr>
|
||||||
|
<tr><td>Cu3</td><td>100 nF</td><td>U3 SHT40 VDD pin</td><td><span class="d d1">🔴</span></td><td>sensor supply</td></tr>
|
||||||
|
<tr><td>Cu4</td><td>100 nF</td><td>reassigned → U18 pin 36 V_BCKP</td><td><span class="d d1">🔴</span></td><td>see the GNSS group — it is already on /3V3–GND, so a board move is all it takes</td></tr>
|
||||||
|
<tr><td>C99</td><td>2.2 nF</td><td>U17/U12 area rail bypass</td><td><span class="d d3">🔵</span></td><td>verify its role in the sch before final spot</td></tr>
|
||||||
|
<tr><td>R41</td><td>10k</td><td>U3/U16 I2C area</td><td><span class="d d3">🔵</span></td><td>pull-up strap</td></tr>
|
||||||
|
<tr><td>R3 D1</td><td>120R · LED</td><td>P9 pins</td><td><span class="d d3">🔵</span></td><td>R3 at the jack</td></tr>
|
||||||
|
<tr><td>R89 R90 R91</td><td>120R ×3</td><td>P10 pins</td><td><span class="d d2">🟠</span></td><td>series at the jack — the wire radiates otherwise</td></tr>
|
||||||
|
<tr><td>D18 R102 R103</td><td>LED (green) · 1k ×2</td><td>3V3 rail, visible spot</td><td><span class="d d3">🔵</span></td><td>power LED</td></tr>
|
||||||
|
<tr><td>TP6 TP7</td><td>GND · 3V3</td><td>anywhere reachable</td><td><span class="d d3">🔵</span></td><td>probe access</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<div class="note"><b>Rail 100 nF rule, restated:</b> every plain 100 nF above pairs with exactly one IC power pin and moves with that IC forever. If you relocate an IC during fine-tuning, its 🔴 rows move in the same drag.</div>
|
||||||
|
|
||||||
|
<h2><span class="no">§9</span>Separation rules</h2>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Keep apart</th><th>Min</th><th>Why</th></tr>
|
||||||
|
<tr><td>GNSS island ↔ any switcher L / SW node</td><td>25 mm</td><td>−167 dBm receiver vs. dV/dt fields</td></tr>
|
||||||
|
<tr><td>GNSS RF run ↔ LTE RF run</td><td>opposite ends</td><td>desense is risk #1; antennas ≥ 20 cm at the enclosure</td></tr>
|
||||||
|
<tr><td>Any crystal ↔ any inductor</td><td>10 mm</td><td>magnetic pickup into the oscillator</td></tr>
|
||||||
|
<tr><td>ADC sense traces ↔ SW nodes</td><td>5 mm + ground between</td><td>tntc/vbat readings ride on µV</td></tr>
|
||||||
|
<tr><td>USB pairs (J9/J11) ↔ switchers</td><td>route as 90 Ω pairs, short</td><td>eye + radiated emissions</td></tr>
|
||||||
|
<tr><td>U26 accel ↔ mounting hole</td><td>≤ 10 mm (close!)</td><td>chassis coupling, not board flex</td></tr>
|
||||||
|
</table></div>
|
||||||
|
|
||||||
|
<h2><span class="no">§10</span>Order of work from here</h2>
|
||||||
|
<ol class="steps">
|
||||||
|
<li><b>Update PCB from Schematic</b> (NTC2 re-net), then fine-tune inside the §1 regions. Field wiring now enters mostly along the north edge + P1 at the SE corner — keep each connector beside its block, and its TVS/filter parts right at the jack, so cable common-mode currents stay off the board core.</li>
|
||||||
|
<li><b>Say the word and I re-add the four zones</b> — F.Cu GND pour, In1 GND (unbroken, especially under both RF runs and the crystals), In2 3V3, B.Cu GND — plus a stitching-via plan: 5 mm grid around RF, via fence along the board edge.</li>
|
||||||
|
<li><b>Route in this order:</b> ① both 50 Ω RF runs (CPWG on F.Cu over In1, JLC7628 ≈ 0.35/0.25 mm — confirm in the JLC calculator and order controlled impedance) · ② the two hot loops and VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm with via farms · ④ USB and ETH pairs · ⑤ sense lines · ⑥ everything else.</li>
|
||||||
|
<li><b>Refill zones, full DRC</b>, then the G2 external review checkpoint before ordering.</li>
|
||||||
|
<li><b>Bench items carried forward:</b> measure U21's 3V3_GNSS rise (F9P ramp window), verify U25's EP against the TI DDA drawing, and the DzG1 jumper check on the fabbed v5.5 boards.</li>
|
||||||
|
</ol>
|
||||||
|
|
||||||
|
<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · updated 05-Sep-2026: U18 V_BCKP (pin 36, /3V3) gets Cu4; C123 clarified as U21-output cap; §8 rows corrected.</p>
|
||||||
|
</div>
|
||||||
398
docs/hardware/EinarBoard-v6_Plan-de-Cobre_ES.html
Normal file
398
docs/hardware/EinarBoard-v6_Plan-de-Cobre_ES.html
Normal file
@ -0,0 +1,398 @@
|
|||||||
|
<title>Plan de Cobre EinarBoard v6</title>
|
||||||
|
<link rel="stylesheet" href="https://fonts.googleapis.com/css2?family=Archivo:wght@500;600;700&family=IBM+Plex+Sans:ital,wght@0,400;0,500;0,600;1,400&family=IBM+Plex+Mono:wght@400;500&display=swap">
|
||||||
|
<style>
|
||||||
|
:root{
|
||||||
|
--paper:#faf8f4; --ink:#1d1c19; --ink2:#5a564d; --line:#e2ddd2;
|
||||||
|
--copper:#a4611f; --copper-soft:#f3e7d6; --plane:#33586e; --plane-soft:#e3ebf0;
|
||||||
|
--crit:#a63b2a; --crit-soft:#f6e5e1; --ok:#43704c;
|
||||||
|
--card:#ffffff; --mono-bg:#f0ece3;
|
||||||
|
}
|
||||||
|
:root:not([data-theme="light"]){ }
|
||||||
|
@media (prefers-color-scheme: dark){
|
||||||
|
:root:not([data-theme="light"]){
|
||||||
|
--paper:#191b1e; --ink:#e3ded4; --ink2:#a09a8d; --line:#33363b;
|
||||||
|
--copper:#d99b52; --copper-soft:#2e2519; --plane:#8fb4c9; --plane-soft:#1f2a31;
|
||||||
|
--crit:#e08373; --crit-soft:#33211d; --ok:#8fbf98;
|
||||||
|
--card:#1f2226; --mono-bg:#25282d;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
:root[data-theme="dark"]{
|
||||||
|
--paper:#191b1e; --ink:#e3ded4; --ink2:#a09a8d; --line:#33363b;
|
||||||
|
--copper:#d99b52; --copper-soft:#2e2519; --plane:#8fb4c9; --plane-soft:#1f2a31;
|
||||||
|
--crit:#e08373; --crit-soft:#33211d; --ok:#8fbf98;
|
||||||
|
--card:#1f2226; --mono-bg:#25282d;
|
||||||
|
}
|
||||||
|
body{background:var(--paper);color:var(--ink);font:400 15.5px/1.55 "IBM Plex Sans",system-ui,sans-serif;margin:0}
|
||||||
|
.wrap{max-width:900px;margin:0 auto;padding:40px 22px 80px}
|
||||||
|
h1,h2,h3{font-family:"Archivo",system-ui,sans-serif;text-wrap:balance;margin:0}
|
||||||
|
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|
||||||
|
.sub{color:var(--ink2);margin:6px 0 0;max-width:64ch}
|
||||||
|
h2{font-size:19px;font-weight:600;margin:44px 0 6px;padding-top:14px;border-top:2px solid var(--copper)}
|
||||||
|
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|
||||||
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|
||||||
|
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|
||||||
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|
||||||
|
.lead{font-size:16.5px}
|
||||||
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table{border-collapse:collapse;width:100%;margin:10px 0;font-size:14px}
|
||||||
|
th{font-family:"Archivo",sans-serif;font-size:11.5px;text-transform:uppercase;letter-spacing:.07em;color:var(--ink2);text-align:left;padding:6px 10px 6px 0;border-bottom:1px solid var(--ink2)}
|
||||||
|
td{padding:6px 10px 6px 0;border-bottom:1px solid var(--line);vertical-align:top}
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||||||
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|
||||||
|
.tblwrap{overflow-x:auto}
|
||||||
|
.loop{background:var(--copper-soft);border-left:3px solid var(--copper);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
|
||||||
|
.loop b:first-child{color:var(--copper)}
|
||||||
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.warn{background:var(--crit-soft);border-left:3px solid var(--crit);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
|
||||||
|
.warn b:first-child{color:var(--crit)}
|
||||||
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.note{background:var(--plane-soft);border-left:3px solid var(--plane);padding:10px 14px;margin:12px 0;border-radius:0 6px 6px 0}
|
||||||
|
.laws{display:grid;grid-template-columns:repeat(auto-fit,minmax(240px,1fr));gap:12px;margin:18px 0}
|
||||||
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|
||||||
|
.law b{display:block;font-family:"Archivo",sans-serif;font-size:14px;margin-bottom:4px;color:var(--copper)}
|
||||||
|
.law p{font-size:13.5px;margin:0;color:var(--ink2)}
|
||||||
|
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|
||||||
|
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|
||||||
|
svg text{font-family:"IBM Plex Mono",monospace}
|
||||||
|
ol.steps{counter-reset:s;list-style:none;padding:0;margin:14px 0}
|
||||||
|
ol.steps li{counter-increment:s;padding:10px 0 10px 44px;position:relative;border-bottom:1px solid var(--line);max-width:76ch}
|
||||||
|
ol.steps li::before{content:counter(s,decimal-leading-zero);position:absolute;left:0;top:10px;font-family:"IBM Plex Mono",monospace;color:var(--copper);font-weight:500}
|
||||||
|
ul{padding-left:20px}
|
||||||
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|
||||||
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.tag{font-family:"Archivo",sans-serif;font-size:10.5px;text-transform:uppercase;letter-spacing:.08em;padding:2px 7px;border-radius:99px;border:1px solid var(--copper);color:var(--copper);white-space:nowrap}
|
||||||
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.tag.q{border-color:var(--plane);color:var(--plane)}
|
||||||
|
.d{font-family:"Archivo",sans-serif;font-size:10px;font-weight:600;letter-spacing:.05em;padding:1px 6px;border-radius:99px;white-space:nowrap}
|
||||||
|
.d1{background:var(--crit-soft);color:var(--crit)}
|
||||||
|
.d2{background:var(--copper-soft);color:var(--copper)}
|
||||||
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.d3{background:var(--plane-soft);color:var(--plane)}
|
||||||
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tr.own td{font-family:"Archivo",sans-serif;font-size:12.5px;font-weight:600;text-transform:uppercase;letter-spacing:.06em;color:var(--copper);border-bottom:2px solid var(--copper);padding-top:18px;white-space:normal}
|
||||||
|
a{color:var(--plane)}
|
||||||
|
</style>
|
||||||
|
<div class="wrap">
|
||||||
|
<h1>Plan de Cobre EinarBoard v6</h1>
|
||||||
|
<p class="sub">Compañero de colocación para el re-layout de 140 × 100 — el dueño de cada capacitor, qué se agrupa junto, y el orden de trabajo EMC. La asignación de capacitores de abajo se calculó a partir del netlist de la tarjeta, no de memoria.</p>
|
||||||
|
|
||||||
|
<div class="note"><b>Renumeración de conectores (03-sep, commit <code>b007c7c</code>):</b> los refs P ahora siguen orden funcional — <code>P1</code> 24V · <code>P2</code> 5V banco de pruebas · <code>P3</code> batería (antes P4) · <code>P4</code> ventilador (antes P6) · <code>P5</code> corte (antes P11) · <code>P6</code> reset (antes P10) · <code>P7</code> sonda NTC 1 (antes P12) · <code>P8</code> sonda NTC 2 (antes P18) · <code>P9</code> LED de panel (antes P8) · <code>P10</code> RGB (antes P14) · <code>P11</code> RS485 (antes P15) · <code>P12</code> RS232 (antes P16). ⚠ La documentación de campo de v5 dice "P12 = NTC" — en v6 ese nombre es el puerto RS232; actualiza la documentación de arneses. La corrección del net NTC2 ya está aplicada y sincronizada.</div>
|
||||||
|
<div class="note"><b>Pendientes conocidos del auto-agrupado:</b> ~54 pequeños traslapes de courtyard, casi todos contra las familias de reguladores heredadas de V5 que conservaron su lugar — <code>L2</code>/<code>D2</code> (bajo el nuevo contorno de U19), <code>L6</code>/<code>DB2</code>/<code>DB3</code>/<code>Q2</code>/<code>Dbk1</code> cerca de U25, <code>C40</code>, <code>R40</code>/<code>R41</code> en Y3. Aparta esos pocos primero y la tarjeta queda limpia.</div>
|
||||||
|
|
||||||
|
<h2><span class="no">§0</span>Tres leyes que deciden la EMC al colocar componentes</h2>
|
||||||
|
<div class="laws">
|
||||||
|
<div class="law"><b>El área del lazo es la antena</b><p>La emisión escala con el área de cada lazo de corriente conmutada. Un lazo caliente cerrado en 1 cm² es ~20 dB más silencioso que el mismo lazo en 10 cm². La colocación resuelve esto; el ruteo no puede rescatar una mala colocación.</p></div>
|
||||||
|
<div class="law"><b>El capacitor más pequeño, más cerca</b><p>Un capacitor filtra hasta la frecuencia que la inductancia de su pista le permite. Ordena los bancos por valor descendente <i>hacia</i> el pin: bulk → 10 µF → 100 nF → pF, con los de pF a 2–3 mm.</p></div>
|
||||||
|
<div class="law"><b>Agresores lejos de las víctimas</b><p>Cuatro conmutadores, un transmisor LTE y un receptor GNSS de −167 dBm en una sola tarjeta. La distancia y un plano de tierra In1 sin cortes son los únicos blindajes de banda ancha que salen gratis.</p></div>
|
||||||
|
</div>
|
||||||
|
|
||||||
|
<h2><span class="no">§1</span>Plano de planta según lo agrupado (NO ETH · NE LTE · SO GNSS · SE potencia)</h2>
|
||||||
|
<figure>
|
||||||
|
<svg viewBox="0 0 700 500" style="max-width:100%;height:auto" role="img" aria-label="Plano de planta actual de la tarjeta de 140 por 100 mm">
|
||||||
|
<rect x="30" y="40" width="630" height="450" fill="none" stroke="var(--ink)" stroke-width="2"/>
|
||||||
|
<text x="30" y="28" font-size="12" fill="var(--ink2)">140 × 100 mm · según agrupado el 03-sep (commit c7d2552) · N = parte superior de la pantalla de KiCad</text>
|
||||||
|
<!-- NO ETH -->
|
||||||
|
<rect x="32" y="42" width="200" height="130" fill="var(--plane-soft)"/>
|
||||||
|
<text x="42" y="64" font-size="13" fill="var(--plane)">NO — ETHERNET</text>
|
||||||
|
<text x="42" y="81" font-size="11" fill="var(--ink2)">J10 RJ45 · U11/U12 · Y1</text>
|
||||||
|
<text x="42" y="96" font-size="11" fill="var(--ink2)">C90–C103 · J11 USB-DFU</text>
|
||||||
|
<!-- NE LTE -->
|
||||||
|
<rect x="440" y="42" width="218" height="200" fill="var(--copper-soft)"/>
|
||||||
|
<text x="452" y="64" font-size="13" fill="var(--copper)">NE — ISLA LTE</text>
|
||||||
|
<text x="452" y="81" font-size="11" fill="var(--ink2)">U20 buck+L20 · banco VBAT</text>
|
||||||
|
<text x="452" y="96" font-size="11" fill="var(--ink2)">U19 A7670SA · K1 · traductores</text>
|
||||||
|
<text x="452" y="111" font-size="11" fill="var(--ink2)">J13 U.FL → esquina NE</text>
|
||||||
|
<!-- MCU -->
|
||||||
|
<rect x="250" y="90" width="170" height="150" fill="none" stroke="var(--line)" stroke-dasharray="5 4"/>
|
||||||
|
<text x="335" y="115" font-size="13" text-anchor="middle" fill="var(--ink)">MCU U16</text>
|
||||||
|
<text x="335" y="132" font-size="11" text-anchor="middle" fill="var(--ink2)">cristales · VCAP · VDDA</text>
|
||||||
|
<text x="335" y="147" font-size="11" text-anchor="middle" fill="var(--ink2)">RCs de medición · U10/Y2 abajo</text>
|
||||||
|
<!-- SO GNSS -->
|
||||||
|
<rect x="32" y="255" width="200" height="233" fill="var(--plane-soft)"/>
|
||||||
|
<text x="42" y="277" font-size="13" fill="var(--plane)">SO — ISLA GNSS</text>
|
||||||
|
<text x="42" y="294" font-size="11" fill="var(--ink2)">U21 LDO · C119–C124</text>
|
||||||
|
<text x="42" y="309" font-size="11" fill="var(--ink2)">U18 F9P · L21 bias tee</text>
|
||||||
|
<text x="42" y="324" font-size="11" fill="var(--ink2)">C143/144/145 · D27 · J12 → borde O</text>
|
||||||
|
<text x="42" y="345" font-size="11" fill="var(--ink2)">U26 acelerómetro en MH6 (barreno SO)</text>
|
||||||
|
<text x="42" y="366" font-size="11" fill="var(--crit)">esquina silenciosa — sin conmutadores</text>
|
||||||
|
<!-- SE potencia -->
|
||||||
|
<rect x="440" y="290" width="218" height="198" fill="var(--copper-soft)"/>
|
||||||
|
<text x="452" y="312" font-size="13" fill="var(--copper)">SE — ENTRADA DE POTENCIA</text>
|
||||||
|
<text x="452" y="329" font-size="11" fill="var(--ink2)">P1 24V · F2 Q23 D32 · partes 24V</text>
|
||||||
|
<text x="452" y="344" font-size="11" fill="var(--ink2)">U25 + L22 + C149–C154</text>
|
||||||
|
<text x="452" y="359" font-size="11" fill="var(--ink2)">U6 LTC4040 + RS1 · ventilador U2 arriba</text>
|
||||||
|
<text x="452" y="374" font-size="11" fill="var(--ink2)">J9 USB · RS232 U15 justo al oeste</text>
|
||||||
|
<!-- separación diagonal -->
|
||||||
|
<line x1="235" y1="370" x2="500" y2="130" stroke="var(--crit)" stroke-dasharray="6 5"/>
|
||||||
|
<text x="368" y="262" font-size="11" text-anchor="middle" fill="var(--crit)" transform="rotate(-42 368 262)">GNSS ↔ LTE en la diagonal · antenas ≥ 20 cm en el gabinete</text>
|
||||||
|
</svg>
|
||||||
|
<figcaption>El estado agrupado tras el commit <code>c7d2552</code> — tus anclas se conservaron (J10, P1, U18, U16, U6, U15, K1, conectores), 160 componentes de soporte empacados por familia. Ajusta libremente dentro de cada región; conserva la diagonal.</figcaption>
|
||||||
|
</figure>
|
||||||
|
|
||||||
|
<h2><span class="no">§2</span>Entrada de potencia vehicular — U25 TPS54360B <span class="tag">lazo caliente</span></h2>
|
||||||
|
<p>Orden de la cadena sobre el cobre, de izquierda a derecha desde P1: <code>F2</code> → <code>Q23</code> (con <code>R119</code>, <code>D33</code> junto a su compuerta) → <code>D32</code> SMCJ33A → capacitores de entrada → <code>U25</code> → <code>D34</code>/<code>L22</code> → capacitores de salida. <code>D10</code> se queda pegado al pin 1 de P1.</p>
|
||||||
|
<div class="loop"><b>El lazo más ruidoso de la tarjeta:</b> C149/C150 (+) → U25 VIN ⟶ U25 SW → cátodo de D34 ⟶ ánodo de D34 → C149/C150 (−). Es un buck no síncrono, así que el lazo de entrada carga todo el di/dt. Pon <code>C149</code>/<code>C150</code> a 2–3 mm de los pines 2/7 de U25, D34 directamente enfrente de ellos, y cierra el lazo sobre tierra sólida. Menos de 1 cm², o se vuelve a hacer.</div>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Valor</th><th>Pertenece a</th><th>Colocación</th></tr>
|
||||||
|
<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>U25 VIN</td><td>a 2–3 mm de los pines 2/7; el lazo caliente</td></tr>
|
||||||
|
<tr><td>C151</td><td>100 µF/50 V</td><td>bulk de entrada de U25</td><td>justo detrás de C149/C150</td></tr>
|
||||||
|
<tr><td>C152</td><td>100 nF</td><td>U25 BOOT</td><td>directamente entre los pines 1–8</td></tr>
|
||||||
|
<tr><td>C153 C154</td><td>47 µF/16 V</td><td>salida 5 V de U25</td><td>en la salida de L22; la toma de FB (R121) va aquí, no en el inductor</td></tr>
|
||||||
|
<tr><td>D34</td><td>B560C</td><td>diodo de rueda libre de U25</td><td>la tierra del ánodo amarra directo a la tierra de C149/C150</td></tr>
|
||||||
|
<tr><td>D32</td><td>SMCJ33A</td><td>supresor de entrada de U25</td><td>entre Q23 y los capacitores de entrada, amarres cortos y gordos</td></tr>
|
||||||
|
<tr><td>R120 · R123 C155 C156 · R121 R122 · R124 R125</td><td>RT · COMP · FB · UVLO (DNP)</td><td>lado analógico de U25</td><td>agrupa en los pines 3–6, del lado opuesto al nodo SW; FB delgado y lejos de L22</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<p>Mantenimiento del riel de 24 V: <code>C10</code>/<code>C22</code> bulk cerca de Q10, <code>C11</code> 100 nF del lado de la carga. Mantén todo el bloque de entrada en una esquina para que el cobre sucio de 24 V nunca cruce la tarjeta.</p>
|
||||||
|
|
||||||
|
<h2><span class="no">§3</span>Respaldo de batería — U6 LTC4040 <span class="tag q">kelvin</span></h2>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Valor</th><th>Pertenece a</th><th>Colocación</th></tr>
|
||||||
|
<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>entrada VEH5V de U6</td><td>en los pines de entrada de U6, después de RS1</td></tr>
|
||||||
|
<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>salida MAIN5V de U6</td><td>del lado de salida U6/Q7</td></tr>
|
||||||
|
<tr><td>C35</td><td>22 µF</td><td>pin BAT de U6 → P3</td><td>cerca de P3; polígono <code>/SW_BAT</code> ≥ 2 mm, <code>/BAT_PLUS</code> ≥ 1.5 mm — el camino de blackout, requisito duro de v6</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<div class="note"><b>RS1 (10 mΩ) es un componente Kelvin:</b> los pines de sensado del LTC4040 deben tomar de las caras de los pads mismos, no de la pista de potencia. Coloca RS1 inmediatamente en U6, con la salida de L22 alimentándolo directo.</div>
|
||||||
|
|
||||||
|
<h2><span class="no">§4</span>Isla LTE — buck U20 + U19 A7670SA <span class="tag">lazo caliente</span></h2>
|
||||||
|
<div class="loop"><b>Segundo lazo caliente:</b> C127/C128 → U20 VIN/GND. Es un buck síncrono, así que el lazo de entrada es el ruidoso — C127 10 µF a 2–3 mm del pin 2 de U20, C128 1 µF aún más cerca. C129 boot entre BOOT–SW, L20 pegado a SW con un vertido de SW mínimo.</div>
|
||||||
|
<p>El banco VBAT es un gradiente en una sola dirección hacia los pines 55/56/57 — el más grande al fondo, el más pequeño tocando el módulo:</p>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Valor</th><th>Orden</th><th>Colocación</th></tr>
|
||||||
|
<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>VBAT de U19 · extremo lejano</td><td>la reserva de ≥300 µF contra caídas (ráfagas de 2.8 A, ≤300 mV de caída)</td></tr>
|
||||||
|
<tr><td>C132 → C133 → C134</td><td>22 µF → 1 µF → 100 nF</td><td>VBAT de U19 · en medio</td><td>escalonando hacia el módulo</td></tr>
|
||||||
|
<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>pines 55/56/57 de U19</td><td>a 2–3 mm — estos mantienen los armónicos de TX fuera de VBAT</td></tr>
|
||||||
|
<tr><td>D22</td><td>SMAJ5.0A</td><td>banco VBAT de U19</td><td>a través de VBAT cerca de C130/C131</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<p>Cobre de VBAT ≥ 3 mm de ancho en todo el trayecto. Alrededor del módulo: <code>C125</code> en el pin 15 (salida 1V8); <code>U22</code> SIM a menos de 5 mm de los pines 30–33, con <code>C126</code> en su pad de VCC y <code>D23–D25</code> PESD en los pads del SIM; <code>U23</code>/<code>U24</code> traductores de nivel entre U19 y el lado del MCU, cada uno con su par de alimentación (<code>C137</code>/<code>C139</code> en 1V8, <code>C138</code>/<code>C140</code> en 3V3) en los pines; <code>Q20–Q22</code> cerca de los pines de control que manejan. <code>J13</code> U.FL en el borde de la tarjeta; la red pi DNP <code>C146</code>/<code>C147</code> (+ su elemento serie) va en línea en el tramo de 50 Ω justo en el conector, <code>D28</code> ESD del lado de tierra del conector.</p>
|
||||||
|
|
||||||
|
<h2><span class="no">§5</span>Isla GNSS — U18 ZED-F9P + LDO U21 <span class="tag q">silenciosa</span></h2>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Valor</th><th>Pertenece a</th><th>Colocación</th></tr>
|
||||||
|
<tr><td>C119</td><td>10 µF</td><td>entrada de U21 (SW_5V)</td><td>en el pin de entrada del LDO</td></tr>
|
||||||
|
<tr><td>C120 C124</td><td>10 µF ×2</td><td>salida U21 → VCC de U18</td><td>uno en la salida de U21, otro en la entrada principal de VCC de U18</td></tr>
|
||||||
|
<tr><td>C121 C122</td><td>100 nF ×2</td><td>pines VCC 33/34 de U18</td><td>uno por pin de alimentación, en el pin</td></tr>
|
||||||
|
<tr><td>C123</td><td>100 nF</td><td>VOUT de U21, junto a C120</td><td>U18 solo tiene dos pines VCC — C123 es el tercero, en la entrada del riel</td></tr>
|
||||||
|
<tr><td>Cu4</td><td>100 nF</td><td>pin 36 de U18, V_BCKP (/3V3!)</td><td>V_BCKP va en el 3V3 siempre-encendido, no en 3V3_GNSS — es a propósito (RTC + efemérides sobreviven cuando U21 se apaga). Necesita su propio capacitor de /3V3 en el pin; C120–C124 están todos en /3V3_GNSS y no le sirven. Reutiliza el Cu4 sobrante.</td></tr>
|
||||||
|
<tr><td>C144 C145</td><td>100 nF · 100 pF</td><td>VCC_RF de U18 · bias tee L21</td><td>del lado de alimentación de L21 — la inyección de alimentación de antena</td></tr>
|
||||||
|
<tr><td>C143</td><td>100 nF RF</td><td>línea RF de J12 (bloqueo DC)</td><td>en línea en el tramo de 50 Ω entre la toma de L21 y J12</td></tr>
|
||||||
|
<tr><td>D27</td><td>ESD9L (≤0.5 pF)</td><td>J12</td><td>en el conector, toma sin stub sobre la línea de RF</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<p>Esta esquina es la víctima: sin conmutador, sin inductor, sin digital rápido a ~25 mm (U25 queda a ~95 mm en el SE, el buck del ventilador a ~130 mm al NE — que siga así); nada más que tierra In1 sólida bajo el módulo y el tramo de RF. <code>TIMEPULSE</code> hacia el MCU es la única línea digital que sale — rútala lejos del camino de RF.</p>
|
||||||
|
|
||||||
|
<h2><span class="no">§6</span>Núcleo MCU — U16 <span class="tag q">cuidado analógico</span></h2>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Valor</th><th>Pertenece a</th><th>Colocación</th></tr>
|
||||||
|
<tr><td>C111</td><td>4.7 µF</td><td>VCAP1 de U16</td><td>≤ 3 mm del pin — el regulador de núcleo, no negociable</td></tr>
|
||||||
|
<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>VDDA de U16</td><td>en el pin VDDA, del lado silencioso, lejos de los conmutadores</td></tr>
|
||||||
|
<tr><td>C105–C108 + C110</td><td>100 nF ×4 + 4.7 µF</td><td>pines VDD de U16</td><td>un 100 nF por pin VDD, bulk cerca</td></tr>
|
||||||
|
<tr><td>C104</td><td>100 nF</td><td>NRST de U16</td><td>en el pin, con el jack de reset P6 ruteado limpio</td></tr>
|
||||||
|
<tr><td>Y3 + C113 C114</td><td>HSE + 15 pF</td><td>pines OSC de U16</td><td>triángulo apretado en los pines, tierra local, ≥10 mm de cualquier inductor</td></tr>
|
||||||
|
<tr><td>Y4 + C115 C116</td><td>LSE 32 kHz + 12 pF</td><td>pines OSC32 de U16</td><td>aún más apretado — oscilador de alta impedancia, protégelo con tierra</td></tr>
|
||||||
|
<tr><td>C5 C7 C9 C24 C157</td><td>100 nF ×5</td><td>pines ADC de U16</td><td>con sus divisores (R42, R126…) en los pines del MCU, no en los jacks — el cable se filtra en el pin</td></tr>
|
||||||
|
</table></div>
|
||||||
|
|
||||||
|
<h2><span class="no">§7</span>El resto de las familias</h2>
|
||||||
|
<ul>
|
||||||
|
<li><b>Ethernet</b> (<code>U11</code>/<code>U12</code>, <code>Y1</code>, <code>C90–C103</code>): un solo bloque, U11 cerca de J10 (los magnéticos van dentro del HR911105A), cristal + 18 pF en los pines, los locales de 3V3_ETH (<code>C92–C94</code>, <code>C98</code>, <code>C102</code>, <code>C103</code>) alrededor de U11. Mantén la región de pares del RJ45 libre de otras rutas.</li>
|
||||||
|
<li><b>RS232</b> (<code>U15</code>): <code>C85–C88</code> son capacitores voladores de la bomba de carga — cargan la corriente de la bomba, así que van pegados a U15; <code>C84</code> 100 nF en su pin de alimentación. P12 (jack RS232) en el borde.</li>
|
||||||
|
<li><b>Puente UART</b> (<code>U10</code>, <code>Y2</code>, <code>C82</code>/<code>C83</code>): capacitores del cristal en los pines, bloque cerca del MCU.</li>
|
||||||
|
<li><b>Buck del ventilador</b> (<code>U2</code>, <code>Cbst1</code>, <code>Ccomp1</code>, <code>C23</code>): un tercer conmutador — trátalo como el lazo del §4, y estaciónalo en el cuarto ruidoso cerca de la entrada de potencia, lejos del GNSS.</li>
|
||||||
|
<li><b>Acelerómetro</b> (<code>U26</code>, <code>C158</code>/<code>C159</code> en VDD/VDDIO, <code>C160</code> bulk): ≤ 10 mm de un barreno de montaje, sobre tarjeta rígida — debe sentir el chasis, no la flexión de la tarjeta.</li>
|
||||||
|
<li><b>Salpicado de rieles</b> (<code>Cu3</code> <code>Cu4</code> <code>C80</code> <code>C81</code> <code>C89</code> <code>C105+</code>…): cada 100 nF en 3V3 se empareja con el pin de alimentación de un solo IC — cuando muevas un IC, su 100 nF se mueve con él. <code>C118</code> 22 µF es el bulk de 3V3 en el regulador.</li>
|
||||||
|
<li><b>Canales NTC</b>: pull-up + filtro (<code>R42</code>+<code>C24</code> → P7, <code>R126</code>+<code>C157</code> → P8) en el MCU; los jacks <code>P7</code>/<code>P8</code> en el borde de arneses.</li>
|
||||||
|
</ul>
|
||||||
|
|
||||||
|
<h2><span class="no">§8</span>Tabla maestra de proximidad — cada discreto, su designador dueño y qué tan cerca</h2>
|
||||||
|
<p>Calculada a partir del netlist actual de la tarjeta (posterior a la renumeración, los 300 footprints), y corregida a mano donde la heurística del netlist eligió un dueño conectado-pero-equivocado (los ESD pertenecen a los conectores, los filtros ADC al MCU, los capacitores de compensación a su regulador). Clases de distancia:</p>
|
||||||
|
<p><span class="d d1">🔴 PEGADO ≤3 mm</span> crítico de lazo — misma tierra de pad, sin via de por medio <span class="d d2">🟠 CERCA ≤5 mm</span> en el pin, pista corta y directa <span class="d d3">🔵 BLOQUE ≤15 mm</span> mismo grupo, orden de ruteo libre</p>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Ref</th><th>Valor</th><th>Pégalo a</th><th></th><th>Por qué</th></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">P1 — entrada 24 V (esquina SE)</td></tr>
|
||||||
|
<tr><td>D10</td><td>SMBJ33A</td><td>pin 1 de P1 (24V_IN)</td><td><span class="d d1">🔴</span></td><td>supresor en el jack, antes que todo lo demás</td></tr>
|
||||||
|
<tr><td>Rig1</td><td>22k</td><td>pin de ignición de P1</td><td><span class="d d1">🔴</span></td><td>elemento serie justo en el jack</td></tr>
|
||||||
|
<tr><td>F2</td><td>2 A lento 1812</td><td>P1 → Q23</td><td><span class="d d3">🔵</span></td><td>primer elemento de la cadena</td></tr>
|
||||||
|
<tr><td>Q23</td><td>IRFR5305</td><td>salida de F2</td><td><span class="d d3">🔵</span></td><td>FET de polaridad inversa, orden de cadena</td></tr>
|
||||||
|
<tr><td>R119 D33</td><td>100k · BZX84C15</td><td>pads G–S de Q23</td><td><span class="d d1">🔴</span></td><td>polarización de compuerta + clamp de 15 V sobre el propio FET</td></tr>
|
||||||
|
<tr><td>D32</td><td>SMCJ33A</td><td>entre Q23 y C149/C150</td><td><span class="d d2">🟠</span></td><td>recorta la línea antes de que el buck la vea</td></tr>
|
||||||
|
<tr><td>Q10</td><td>IRFR5305</td><td>rama de 24 V de P1</td><td><span class="d d3">🔵</span></td><td>FET del riel 24 V heredado (alimenta U2 + K1)</td></tr>
|
||||||
|
<tr><td>Rrp1 DzG1</td><td>10k · BZX84C15</td><td>pads G–S de Q10</td><td><span class="d d1">🔴</span></td><td>red de compuerta — la pieza del chequeo con jumper de v5.5</td></tr>
|
||||||
|
<tr><td>C10 C22</td><td>47 µF/50 V · 22 µF/50 V</td><td>lado de carga de Q10 (/24V)</td><td><span class="d d3">🔵</span></td><td>bulk del riel de 24 V</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U25 — buck vehicular TPS54360B</td></tr>
|
||||||
|
<tr><td>C149 C150</td><td>2.2 µF/100 V</td><td>pines 2/7 de U25 (VIN–GND)</td><td><span class="d d1">🔴</span></td><td>EL lazo caliente de la tarjeta</td></tr>
|
||||||
|
<tr><td>D34</td><td>B560C</td><td>SW de U25 + tierra de C149</td><td><span class="d d1">🔴</span></td><td>cierra el lazo caliente</td></tr>
|
||||||
|
<tr><td>C151</td><td>100 µF/50 V</td><td>detrás de C149/C150</td><td><span class="d d2">🟠</span></td><td>bulk de entrada</td></tr>
|
||||||
|
<tr><td>C152</td><td>100 nF</td><td>BOOT de U25 (pines 1–8)</td><td><span class="d d1">🔴</span></td><td>capacitor de bootstrap</td></tr>
|
||||||
|
<tr><td>L22</td><td>10 µH SRP1265A</td><td>pin SW de U25</td><td><span class="d d2">🟠</span></td><td>cobre de SW mínimo</td></tr>
|
||||||
|
<tr><td>C153 C154</td><td>47 µF/16 V</td><td>pad de salida de L22</td><td><span class="d d2">🟠</span></td><td>capacitores de salida VEH5V; FB toma de aquí</td></tr>
|
||||||
|
<tr><td>R121 R122</td><td>53.6k · 10.2k</td><td>pin FB de U25, toma en C153</td><td><span class="d d2">🟠</span></td><td>pista delgada, lejos del campo de L22</td></tr>
|
||||||
|
<tr><td>R123 C155 C156</td><td>13k · 6.8 nF · 39 pF</td><td>pin COMP de U25</td><td><span class="d d2">🟠</span></td><td>compensación — lado silencioso, tierra corta</td></tr>
|
||||||
|
<tr><td>R120</td><td>162k</td><td>pin RT de U25</td><td><span class="d d2">🟠</span></td><td>fija la frecuencia, tierra corta</td></tr>
|
||||||
|
<tr><td>R124 R125</td><td>UVLO (DNP)</td><td>pin EN de U25</td><td><span class="d d2">🟠</span></td><td>el divisor aterriza aquí si se monta</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U6 — respaldo de batería LTC4040 (+P3)</td></tr>
|
||||||
|
<tr><td>RS1</td><td>10 mΩ 1%</td><td>pines de sensado de U6</td><td><span class="d d1">🔴</span></td><td>Kelvin — el sensado sale de las caras de los pads</td></tr>
|
||||||
|
<tr><td>L6</td><td>2.2 µH/8 A</td><td>pines SW de U6</td><td><span class="d d1">🔴</span></td><td>lazo del cargador/boost apretado</td></tr>
|
||||||
|
<tr><td>C30 C31 C78</td><td>10 µF · 2.2 µF · 220 µF</td><td>VIN de U6, después de RS1</td><td><span class="d d2">🟠</span></td><td>banco VEH5V en los pines de entrada</td></tr>
|
||||||
|
<tr><td>C32 C33 C34</td><td>47 µF ×2 · 10 µF</td><td>salida MAIN5V de U6 / Q7</td><td><span class="d d2">🟠</span></td><td>banco de salida</td></tr>
|
||||||
|
<tr><td>C35</td><td>22 µF</td><td>pin BAT de U6 → P3</td><td><span class="d d2">🟠</span></td><td>sobre el cobre ancho de /BAT_PLUS</td></tr>
|
||||||
|
<tr><td>Q7</td><td>AO4406A</td><td>lado gate/PowerPath de U6</td><td><span class="d d2">🟠</span></td><td>el interruptor de blackout</td></tr>
|
||||||
|
<tr><td>R50</td><td>825R 1%</td><td>pin PROG de U6</td><td><span class="d d1">🔴</span></td><td>resistencia de precisión de programa de corriente</td></tr>
|
||||||
|
<tr><td>R51 R52</td><td>270k · 100k</td><td>pin PFI de U6</td><td><span class="d d2">🟠</span></td><td>divisor de falla de alimentación</td></tr>
|
||||||
|
<tr><td>R53 R54</td><td>499k · 100k</td><td>pin FB de U6</td><td><span class="d d2">🟠</span></td><td>retroalimentación del boost</td></tr>
|
||||||
|
<tr><td>R55</td><td>10k 1%</td><td>pin NTC de U6</td><td><span class="d d2">🟠</span></td><td>divisor del termistor del pack (la sonda entra por P3)</td></tr>
|
||||||
|
<tr><td>JP2 JP3 JP4</td><td>straps F</td><td>pines F0/F1/F2 de U6</td><td><span class="d d3">🔵</span></td><td>straps lógicos</td></tr>
|
||||||
|
<tr><td>R56 R57 R58</td><td>100k ×3</td><td>ruta U6 ↔ U16</td><td><span class="d d3">🔵</span></td><td>pulls de estado/habilitación, en cualquier punto de la línea</td></tr>
|
||||||
|
<tr><td>TP1 TP2</td><td>CLPROG · PFO</td><td>borde del bloque de U6</td><td><span class="d d3">🔵</span></td><td>acceso de medición</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U2 — buck del ventilador MP1584 (+P4)</td></tr>
|
||||||
|
<tr><td>C11</td><td>100 nF</td><td>pin VIN de U2</td><td><span class="d d1">🔴</span></td><td>lazo de entrada no síncrono (bulk C10/C22 detrás)</td></tr>
|
||||||
|
<tr><td>Dbk1</td><td>SS34</td><td>SW de U2 + tierra de entrada</td><td><span class="d d1">🔴</span></td><td>diodo de rueda libre — mismo lazo</td></tr>
|
||||||
|
<tr><td>Cbst1</td><td>10 nF</td><td>BOOT–SW de U2</td><td><span class="d d1">🔴</span></td><td>capacitor de bootstrap</td></tr>
|
||||||
|
<tr><td>L2</td><td>10 µH</td><td>SW de U2</td><td><span class="d d2">🟠</span></td><td>cobre de SW mínimo</td></tr>
|
||||||
|
<tr><td>C23</td><td>22 µF/16 V</td><td>salida de L2 → P4</td><td><span class="d d2">🟠</span></td><td>capacitor de salida 5V_FAN</td></tr>
|
||||||
|
<tr><td>R20 R21</td><td>100k · 19.1k</td><td>FB de U2, toma en C23</td><td><span class="d d2">🟠</span></td><td>divisor de retroalimentación</td></tr>
|
||||||
|
<tr><td>Rcomp1 Ccomp1</td><td>40.2k · 2.2 nF</td><td>pin COMP de U2</td><td><span class="d d2">🟠</span></td><td>compensación</td></tr>
|
||||||
|
<tr><td>Rfreq1</td><td>100k</td><td>pin FREQ de U2</td><td><span class="d d2">🟠</span></td><td>fija la frecuencia</td></tr>
|
||||||
|
<tr><td>Ren1 Ren2</td><td>100k · 20k</td><td>pin EN de U2</td><td><span class="d d3">🔵</span></td><td>divisor de habilitación</td></tr>
|
||||||
|
<tr><td>D2</td><td>SS34</td><td>pines de P4</td><td><span class="d d1">🔴</span></td><td>flyback justo en el jack del ventilador</td></tr>
|
||||||
|
<tr><td>Q2 Rgs1</td><td>AO3400A · 100k</td><td>retorno de P4 · Rgs1 en G–S de Q2</td><td><span class="d d2">🟠</span></td><td>interruptor de lado bajo en el jack, resistencia G–S pegada</td></tr>
|
||||||
|
<tr><td>Q5 Rg1</td><td>MMBT3904 · 100R</td><td>compuerta de Q2</td><td><span class="d d3">🔵</span></td><td>etapa de manejo de compuerta</td></tr>
|
||||||
|
<tr><td>JP1</td><td>0R</td><td>enlace 5V_FAN de P4</td><td><span class="d d3">🔵</span></td><td>enlace para medir corriente</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U20 — buck del módem AP64350</td></tr>
|
||||||
|
<tr><td>C127 C128</td><td>10 µF · 1 µF</td><td>pin VIN 2 de U20</td><td><span class="d d1">🔴</span></td><td>lazo de entrada síncrono — el de 1 µF, el más cercano de todos</td></tr>
|
||||||
|
<tr><td>C129</td><td>100 nF</td><td>BOOT–SW de U20</td><td><span class="d d1">🔴</span></td><td>capacitor de bootstrap</td></tr>
|
||||||
|
<tr><td>L20</td><td>4.7 µH/5 A</td><td>SW de U20</td><td><span class="d d2">🟠</span></td><td>cobre de SW mínimo</td></tr>
|
||||||
|
<tr><td>D21</td><td>PMEG3050EP</td><td>alimentación VIN de U20</td><td><span class="d d2">🟠</span></td><td>ORing de entrada</td></tr>
|
||||||
|
<tr><td>D20</td><td>SS34</td><td>rama 24 V → entrada de U20</td><td><span class="d d3">🔵</span></td><td>diodo de alimentación</td></tr>
|
||||||
|
<tr><td>R110 R111</td><td>75k · 20k</td><td>pin FB de U20</td><td><span class="d d2">🟠</span></td><td>divisor de retroalimentación</td></tr>
|
||||||
|
<tr><td>R116 C141 C142</td><td>14k · 3.3 nF · 47 pF</td><td>pin COMP de U20</td><td><span class="d d2">🟠</span></td><td>compensación</td></tr>
|
||||||
|
<tr><td>R117</td><td>200k 1%</td><td>pin RT de U20</td><td><span class="d d2">🟠</span></td><td>fija la frecuencia</td></tr>
|
||||||
|
<tr><td>R113</td><td>100k</td><td>pin EN de U20</td><td><span class="d d3">🔵</span></td><td>pull de habilitación</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U19 — módem A7670SA (+U22 SIM · U23/U24 · K1 · J13)</td></tr>
|
||||||
|
<tr><td>C135 C136</td><td>33 pF · 10 pF</td><td>pines 55/56/57 de U19</td><td><span class="d d1">🔴</span></td><td>filtros de armónicos de TX — los más cercanos del banco</td></tr>
|
||||||
|
<tr><td>C134 C133 C132</td><td>100 nF → 1 µF → 22 µF</td><td>escalonando desde esos pines</td><td><span class="d d2">🟠</span></td><td>el gradiente</td></tr>
|
||||||
|
<tr><td>C130 C131</td><td>220 µF/10 V ×2</td><td>extremo lejano del banco VBAT de U19</td><td><span class="d d3">🔵</span></td><td>reserva de ráfagas de ≥300 µF</td></tr>
|
||||||
|
<tr><td>D22</td><td>SMAJ5.0A</td><td>en C130/C131</td><td><span class="d d2">🟠</span></td><td>clamp de VBAT</td></tr>
|
||||||
|
<tr><td>R112</td><td>1k</td><td>lado VBAT de U19</td><td><span class="d d3">🔵</span></td><td>sangrado/monitoreo</td></tr>
|
||||||
|
<tr><td>C125</td><td>2.2 µF</td><td>pin 15 de U19 (salida 1V8)</td><td><span class="d d1">🔴</span></td><td>capacitor de salida del LDO</td></tr>
|
||||||
|
<tr><td>U22</td><td>SIM (huella por definir)</td><td>pines 30–33 de U19, ≤5 mm</td><td><span class="d d2">🟠</span></td><td>bus SIM sin blindaje</td></tr>
|
||||||
|
<tr><td>C126</td><td>100 nF</td><td>pad VCC de U22</td><td><span class="d d1">🔴</span></td><td>alimentación del SIM</td></tr>
|
||||||
|
<tr><td>D23 D24 D25</td><td>PESD5V0S1BA</td><td>pads SIM de U22</td><td><span class="d d1">🔴</span></td><td>ESD en el zócalo, no a media ruta</td></tr>
|
||||||
|
<tr><td>U23 U24</td><td>74LVC2T45</td><td>entre U19 y U16</td><td><span class="d d3">🔵</span></td><td>los traductores de nivel van sobre el camino</td></tr>
|
||||||
|
<tr><td>C137 C139</td><td>100 nF</td><td>pines 1V8 de U23/U24</td><td><span class="d d1">🔴</span></td><td>par de alimentación, uno cada uno</td></tr>
|
||||||
|
<tr><td>C138 C140</td><td>100 nF</td><td>pines 3V3 de U23/U24</td><td><span class="d d1">🔴</span></td><td>par de alimentación, uno cada uno</td></tr>
|
||||||
|
<tr><td>Q20 R114</td><td>2N7002 · 100k</td><td>lado PWRKEY de U19</td><td><span class="d d3">🔵</span></td><td>driver open-drain</td></tr>
|
||||||
|
<tr><td>Q21 R115</td><td>2N7002 · 100k</td><td>lado RESET de U19</td><td><span class="d d3">🔵</span></td><td>driver open-drain</td></tr>
|
||||||
|
<tr><td>R109 Q22 Rmled1 D4G1</td><td>cadena NETLIGHT</td><td>pin netlight de U19 → LED en punto visible</td><td><span class="d d3">🔵</span></td><td>driver del LED de estado</td></tr>
|
||||||
|
<tr><td>R106 R107 R108</td><td>100R · 0R ×2</td><td>extremos de línea de U23/U24</td><td><span class="d d3">🔵</span></td><td>elementos serie del UART</td></tr>
|
||||||
|
<tr><td>TP8</td><td>USB_BOOT</td><td>pin BOOT de U19</td><td><span class="d d3">🔵</span></td><td>acceso de medición</td></tr>
|
||||||
|
<tr><td>R118 C146 C147</td><td>0R · pi DNP</td><td>en línea en el tramo de 50 Ω, pad RF de U19 → J13</td><td><span class="d d1">🔴</span></td><td>asientos de acoplamiento — cero stubs</td></tr>
|
||||||
|
<tr><td>D28</td><td>ESD9L</td><td>J13</td><td><span class="d d1">🔴</span></td><td>en el conector, sin stub</td></tr>
|
||||||
|
<tr><td>D6</td><td>1N4148W</td><td>pines de bobina de K1</td><td><span class="d d1">🔴</span></td><td>flyback a través de la bobina</td></tr>
|
||||||
|
<tr><td>Q6 R2 C101</td><td>MMBT3904 · 10k · 22 µF</td><td>lado de bobina de K1</td><td><span class="d d2">🟠</span></td><td>driver del relevador + capacitor de la bobina</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U18 — GNSS ZED-F9P (+LDO U21 · J12)</td></tr>
|
||||||
|
<tr><td>C121 C122</td><td>100 nF ×2</td><td>pines VCC 33/34 de U18, uno cada uno</td><td><span class="d d1">🔴</span></td><td>desacoplo por pin</td></tr>
|
||||||
|
<tr><td>C123</td><td>100 nF</td><td>VOUT de U21 junto a C120</td><td><span class="d d2">🟠</span></td><td>tercer 100 nF — entrada del riel, no un tercer pin VCC</td></tr>
|
||||||
|
<tr><td>Cu4</td><td>100 nF</td><td>pin 36 de U18, V_BCKP — en /3V3</td><td><span class="d d1">🔴</span></td><td>único capacitor de /3V3 en la esquina; el riel de respaldo sigue vivo cuando U21 se apaga</td></tr>
|
||||||
|
<tr><td>C120 C124</td><td>10 µF ×2</td><td>salida de U21 · entrada VCC de U18</td><td><span class="d d1">🔴</span></td><td>estabilidad del LDO + bulk local</td></tr>
|
||||||
|
<tr><td>C119</td><td>10 µF</td><td>pin de entrada de U21</td><td><span class="d d1">🔴</span></td><td>entrada del LDO</td></tr>
|
||||||
|
<tr><td>C3 C40</td><td>47 µF · 22 µF</td><td>alimentación SW_5V cerca de U21</td><td><span class="d d2">🟠</span></td><td>bulk aguas arriba</td></tr>
|
||||||
|
<tr><td>Q1</td><td>AO3401A</td><td>aguas arriba de U21 en SW_5V</td><td><span class="d d3">🔵</span></td><td>interruptor del riel</td></tr>
|
||||||
|
<tr><td>R105</td><td>10k</td><td>pull-up de U18</td><td><span class="d d3">🔵</span></td><td>strap</td></tr>
|
||||||
|
<tr><td>L21 C144 C145</td><td>68 nH · 100 nF · 100 pF</td><td>toma del bias tee sobre el tramo de 50 Ω</td><td><span class="d d1">🔴</span></td><td>inyección de alimentación de antena</td></tr>
|
||||||
|
<tr><td>C143</td><td>100 nF RF</td><td>en línea, toma de L21 → J12</td><td><span class="d d1">🔴</span></td><td>bloqueo de DC</td></tr>
|
||||||
|
<tr><td>D27</td><td>ESD9L ≤0.5 pF</td><td>J12</td><td><span class="d d1">🔴</span></td><td>en el conector, sin stub</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U16 — MCU STM32 (+Y3/Y4 · USB J11/J9 · jacks de medición)</td></tr>
|
||||||
|
<tr><td>C111</td><td>4.7 µF</td><td>pin VCAP1 de U16</td><td><span class="d d1">🔴</span></td><td>regulador de núcleo — no negociable</td></tr>
|
||||||
|
<tr><td>R104</td><td>10R</td><td>alimentación VDDA de U16</td><td><span class="d d1">🔴</span></td><td>elemento serie del filtro analógico</td></tr>
|
||||||
|
<tr><td>C109 C112</td><td>100 nF · 1 µF</td><td>pin VDDA de U16, tras R104</td><td><span class="d d1">🔴</span></td><td>desacoplo analógico</td></tr>
|
||||||
|
<tr><td>C105 C106 C107 C108</td><td>100 nF ×4</td><td>uno por pin VDD de U16</td><td><span class="d d1">🔴</span></td><td>la pasada de netlist estacionó C106–C108 cerca de U3 — son de U16, regrésalos</td></tr>
|
||||||
|
<tr><td>C110</td><td>4.7 µF</td><td>bulk VDD de U16</td><td><span class="d d2">🟠</span></td><td>reserva local</td></tr>
|
||||||
|
<tr><td>C104</td><td>100 nF</td><td>pin NRST de U16</td><td><span class="d d1">🔴</span></td><td>el jack P6 solo se rutea hasta él</td></tr>
|
||||||
|
<tr><td>Y3 C113 C114</td><td>25 MHz · 15 pF</td><td>pines OSC de U16</td><td><span class="d d1">🔴</span></td><td>triángulo apretado, tierra local</td></tr>
|
||||||
|
<tr><td>Y4 C115 C116</td><td>32.768 kHz · 12 pF</td><td>pines OSC32 de U16</td><td><span class="d d1">🔴</span></td><td>más apretado aún — oscilador de alta impedancia</td></tr>
|
||||||
|
<tr><td>R5 R6 C5</td><td>10k ×2 · 100 nF</td><td>pin ADC BAT_SENSE de U16</td><td><span class="d d2">🟠</span></td><td>divisor + filtro en el pin</td></tr>
|
||||||
|
<tr><td>R7 R8 C7</td><td>10k ×2 · 100 nF</td><td>pin ADC 5V_SENSE de U16</td><td><span class="d d2">🟠</span></td><td>divisor + filtro en el pin</td></tr>
|
||||||
|
<tr><td>Rig2 Rigb1 C9 D5</td><td>22k · 3.3k · 100 nF · BAT54</td><td>pin ADC IGN_SENSE de U16</td><td><span class="d d2">🟠</span></td><td>divisor + filtro + clamp en el pin</td></tr>
|
||||||
|
<tr><td>R42 C24</td><td>10k 1% · 100 nF</td><td>pin ADC NTC1 de U16 — P7 es solo el jack</td><td><span class="d d2">🟠</span></td><td>el cable de la sonda se filtra en el pin</td></tr>
|
||||||
|
<tr><td>R126 C157</td><td>10k 1% · 100 nF</td><td>pin ADC NTC2 de U16 (PC4) — P8 es solo el jack</td><td><span class="d d2">🟠</span></td><td>misma regla</td></tr>
|
||||||
|
<tr><td>R98 R99</td><td>10k ×2</td><td>straps BOOT de U16</td><td><span class="d d3">🔵</span></td><td>en cualquier parte del bloque</td></tr>
|
||||||
|
<tr><td>Rdfu1</td><td>22k</td><td>USART1_RX de U16</td><td><span class="d d3">🔵</span></td><td>elemento serie</td></tr>
|
||||||
|
<tr><td>TP3 TP4 TP5</td><td>SWDIO · SWCLK · NRST</td><td>lado de U16 / lado de P6</td><td><span class="d d3">🔵</span></td><td>acceso de medición</td></tr>
|
||||||
|
<tr><td>R1 R40 R56</td><td>1k · 1k · 100k</td><td>líneas de control U16 → bloques de potencia</td><td><span class="d d3">🔵</span></td><td>en cualquier punto de la ruta</td></tr>
|
||||||
|
<tr><td>D17</td><td>LED (azul)</td><td>cerca de PC13 de U16, visible</td><td><span class="d d3">🔵</span></td><td>LED de latido</td></tr>
|
||||||
|
<tr><td>Q4 Rled1</td><td>AO3400A · 10k</td><td>cerca del borde P9/P10</td><td><span class="d d3">🔵</span></td><td>driver del LED externo</td></tr>
|
||||||
|
<tr><td>D13</td><td>SS34</td><td>VBUS de J11</td><td><span class="d d2">🟠</span></td><td>ORing de VBUS</td></tr>
|
||||||
|
<tr><td>D14 D15 D16</td><td>PESD5V0S1BA</td><td>pads de J11 (DP/DM/VBUS)</td><td><span class="d d1">🔴</span></td><td>ESD en el jack — nunca a media ruta</td></tr>
|
||||||
|
<tr><td>R100 R101</td><td>5.1k</td><td>pads CC de J11</td><td><span class="d d1">🔴</span></td><td>identificación de sink USB-C</td></tr>
|
||||||
|
<tr><td>Rcc1 Rcc2</td><td>5.1k</td><td>pads CC de J9</td><td><span class="d d1">🔴</span></td><td>identificación de sink USB-C</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U11 — Ethernet W5500 (+buck U12 · Y1 · J10)</td></tr>
|
||||||
|
<tr><td>C90</td><td>10 µF</td><td>pin TOCAP de U11</td><td><span class="d d1">🔴</span></td><td>capacitor del regulador interno</td></tr>
|
||||||
|
<tr><td>C91</td><td>4.7 µF</td><td>pin 1V2 de U11</td><td><span class="d d1">🔴</span></td><td>riel de núcleo</td></tr>
|
||||||
|
<tr><td>C92 C93 C98</td><td>100 nF ×3</td><td>pines VCC de U11, uno cada uno</td><td><span class="d d1">🔴</span></td><td>desacoplo por pin</td></tr>
|
||||||
|
<tr><td>C94 C102</td><td>10 µF · 22 µF</td><td>entrada de alimentación de U11</td><td><span class="d d2">🟠</span></td><td>bulk local</td></tr>
|
||||||
|
<tr><td>Y1 C95 C96</td><td>25 MHz · 18 pF</td><td>pines XI/XO de U11</td><td><span class="d d1">🔴</span></td><td>triángulo apretado</td></tr>
|
||||||
|
<tr><td>R83</td><td>12.4k 1%</td><td>pin RSET de U11</td><td><span class="d d1">🔴</span></td><td>polarización de precisión — corta, tierra limpia</td></tr>
|
||||||
|
<tr><td>R84</td><td>10k</td><td>PMODE de U11</td><td><span class="d d3">🔵</span></td><td>strap</td></tr>
|
||||||
|
<tr><td>R92 R93</td><td>49.9R 1%</td><td>pines TX de U11 → J10</td><td><span class="d d1">🔴</span></td><td>terminaciones de línea</td></tr>
|
||||||
|
<tr><td>R94 R95 C97</td><td>49.9R ×2 · 6.8 nF</td><td>tomas centrales de J10</td><td><span class="d d1">🔴</span></td><td>red Bob Smith / RCT en el magjack</td></tr>
|
||||||
|
<tr><td>C103</td><td>100 µF/6.3 V</td><td>alimentación 3V3 de J10</td><td><span class="d d2">🟠</span></td><td>bulk de los magnéticos</td></tr>
|
||||||
|
<tr><td>R96 R97</td><td>330R</td><td>pines LED de J10</td><td><span class="d d3">🔵</span></td><td>LEDs de enlace/actividad</td></tr>
|
||||||
|
<tr><td>D11</td><td>SS34</td><td>SW de U12 + tierra de entrada</td><td><span class="d d1">🔴</span></td><td>diodo de rueda libre del buck ETH</td></tr>
|
||||||
|
<tr><td>C100</td><td>10 nF</td><td>BOOT de U12</td><td><span class="d d1">🔴</span></td><td>capacitor de bootstrap</td></tr>
|
||||||
|
<tr><td>L8</td><td>10 µH/2 A</td><td>SW de U12</td><td><span class="d d2">🟠</span></td><td>cobre de SW mínimo</td></tr>
|
||||||
|
<tr><td>R85 R86 R87 R88</td><td>FREQ · COMP · FB</td><td>pines de U12</td><td><span class="d d2">🟠</span></td><td>mantenimiento en el IC</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U17 — LDO 3V3 AMS1117</td></tr>
|
||||||
|
<tr><td>C117</td><td>10 µF</td><td>pin IN de U17</td><td><span class="d d1">🔴</span></td><td>entrada del LDO</td></tr>
|
||||||
|
<tr><td>C118</td><td>22 µF/16 V</td><td>pin OUT de U17</td><td><span class="d d1">🔴</span></td><td>salida del LDO / bulk de 3V3</td></tr>
|
||||||
|
<tr><td>D12</td><td>SS34</td><td>alimentación de entrada de U17</td><td><span class="d d2">🟠</span></td><td>ORing de alimentación</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">Bloque serial — U15 RS232 · U10 UART · U14 RS485 · expansor U13</td></tr>
|
||||||
|
<tr><td>C85 C86 C87 C88</td><td>100 nF ×4</td><td>pines de bomba de U15, pegados al IC</td><td><span class="d d1">🔴</span></td><td>los capacitores voladores cargan la corriente de la bomba</td></tr>
|
||||||
|
<tr><td>C84</td><td>100 nF</td><td>pin VCC de U15</td><td><span class="d d1">🔴</span></td><td>alimentación</td></tr>
|
||||||
|
<tr><td>Y2 C82 C83</td><td>1.8432 MHz · 22 pF</td><td>pines XTAL de U10</td><td><span class="d d1">🔴</span></td><td>triángulo apretado</td></tr>
|
||||||
|
<tr><td>R30 R31</td><td>4.7k</td><td>lado U10 del bus I2C</td><td><span class="d d3">🔵</span></td><td>pull-ups del bus</td></tr>
|
||||||
|
<tr><td>R80 R81</td><td>10k</td><td>RST/IRQ de U10</td><td><span class="d d3">🔵</span></td><td>pulls</td></tr>
|
||||||
|
<tr><td>C81 C89</td><td>100 nF ×2</td><td>VCC de U14 (uno queda de repuesto)</td><td><span class="d d1">🔴</span></td><td>alimentación</td></tr>
|
||||||
|
<tr><td>R82 JP5</td><td>120R · strap</td><td>jack RS485 P11</td><td><span class="d d2">🟠</span></td><td>la terminación vive en el conector</td></tr>
|
||||||
|
<tr><td>C80</td><td>100 nF</td><td>pin VCC de U13</td><td><span class="d d1">🔴</span></td><td>alimentación</td></tr>
|
||||||
|
<tr><td>RB1 RB2 RB3 RB4<br>DB1 DB2 DB3 DB4</td><td>120R + LED ×4</td><td>salidas de U13 → LEDs en el borde visible</td><td><span class="d d3">🔵</span></td><td>la pasada de netlist estacionó DB1–DB4 en U25 — pertenecen a U13</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">U26 — acelerómetro SC7A20 (en MH6)</td></tr>
|
||||||
|
<tr><td>C158 C159</td><td>100 nF ×2</td><td>pines VDD/VDDIO de U26</td><td><span class="d d1">🔴</span></td><td>uno por pin de alimentación</td></tr>
|
||||||
|
<tr><td>C160</td><td>10 µF</td><td>bulk de U26</td><td><span class="d d2">🟠</span></td><td>reserva local; U26 mismo a ≤10 mm de MH6</td></tr>
|
||||||
|
|
||||||
|
<tr class="own"><td colspan="5">Panel · sensores · sobrantes</td></tr>
|
||||||
|
<tr><td>Cu3</td><td>100 nF</td><td>pin VDD del SHT40 U3</td><td><span class="d d1">🔴</span></td><td>alimentación del sensor</td></tr>
|
||||||
|
<tr><td>Cu4</td><td>100 nF</td><td>reasignado → pin 36 de U18, V_BCKP</td><td><span class="d d1">🔴</span></td><td>ver el grupo GNSS — ya está en /3V3–GND, así que basta moverlo en la tarjeta</td></tr>
|
||||||
|
<tr><td>C99</td><td>2.2 nF</td><td>bypass de riel zona U17/U12</td><td><span class="d d3">🔵</span></td><td>verifica su papel en el esquemático antes del lugar final</td></tr>
|
||||||
|
<tr><td>R41</td><td>10k</td><td>zona I2C U3/U16</td><td><span class="d d3">🔵</span></td><td>strap de pull-up</td></tr>
|
||||||
|
<tr><td>R3 D1</td><td>120R · LED</td><td>pines de P9</td><td><span class="d d3">🔵</span></td><td>R3 en el jack</td></tr>
|
||||||
|
<tr><td>R89 R90 R91</td><td>120R ×3</td><td>pines de P10</td><td><span class="d d2">🟠</span></td><td>serie en el jack — si no, el cable radia</td></tr>
|
||||||
|
<tr><td>D18 R102 R103</td><td>LED (verde) · 1k ×2</td><td>riel 3V3, punto visible</td><td><span class="d d3">🔵</span></td><td>LED de encendido</td></tr>
|
||||||
|
<tr><td>TP6 TP7</td><td>GND · 3V3</td><td>donde queden accesibles</td><td><span class="d d3">🔵</span></td><td>acceso de medición</td></tr>
|
||||||
|
</table></div>
|
||||||
|
<div class="note"><b>La regla del 100 nF de riel, otra vez:</b> cada 100 nF simple de arriba se empareja con exactamente un pin de alimentación de un IC y se mueve con ese IC para siempre. Si reubicas un IC durante el ajuste fino, sus filas 🔴 se mueven en el mismo arrastre.</div>
|
||||||
|
|
||||||
|
<h2><span class="no">§9</span>Reglas de separación</h2>
|
||||||
|
<div class="tblwrap"><table>
|
||||||
|
<tr><th>Mantén separados</th><th>Mín</th><th>Por qué</th></tr>
|
||||||
|
<tr><td>Isla GNSS ↔ cualquier L / nodo SW de conmutador</td><td>25 mm</td><td>receptor de −167 dBm contra campos de dV/dt</td></tr>
|
||||||
|
<tr><td>Tramo RF GNSS ↔ tramo RF LTE</td><td>extremos opuestos</td><td>la desensibilización es el riesgo #1; antenas ≥ 20 cm en el gabinete</td></tr>
|
||||||
|
<tr><td>Cualquier cristal ↔ cualquier inductor</td><td>10 mm</td><td>acoplamiento magnético hacia el oscilador</td></tr>
|
||||||
|
<tr><td>Pistas de sensado ADC ↔ nodos SW</td><td>5 mm + tierra en medio</td><td>las lecturas tntc/vbat viajan sobre µV</td></tr>
|
||||||
|
<tr><td>Pares USB (J9/J11) ↔ conmutadores</td><td>rutea como pares de 90 Ω, cortos</td><td>ojo de la señal + emisiones radiadas</td></tr>
|
||||||
|
<tr><td>Acelerómetro U26 ↔ barreno de montaje</td><td>≤ 10 mm (¡cerca!)</td><td>acoplamiento al chasis, no a la flexión de la tarjeta</td></tr>
|
||||||
|
</table></div>
|
||||||
|
|
||||||
|
<h2><span class="no">§10</span>Orden de trabajo desde aquí</h2>
|
||||||
|
<ol class="steps">
|
||||||
|
<li><b>Update PCB from Schematic</b> (re-net de NTC2), luego ajuste fino dentro de las regiones del §1. El cableado de campo ahora entra sobre todo por el borde norte + P1 en la esquina SE — mantén cada conector junto a su bloque, y sus TVS/filtros justo en el jack, para que las corrientes de modo común de los cables no entren al núcleo de la tarjeta.</li>
|
||||||
|
<li><b>Con una palabra tuya reintegro las cuatro zonas</b> — vertido GND en F.Cu, GND en In1 (sin cortes, sobre todo bajo ambos tramos de RF y los cristales), 3V3 en In2, GND en B.Cu — más un plan de vias de costura: rejilla de 5 mm alrededor de RF, cerca de vias a lo largo del borde de la tarjeta.</li>
|
||||||
|
<li><b>Rutea en este orden:</b> ① ambos tramos de RF de 50 Ω (CPWG en F.Cu sobre In1, JLC7628 ≈ 0.35/0.25 mm — confírmalo en la calculadora de JLC y pide impedancia controlada) · ② los dos lazos calientes y VBAT ≥ 3 mm · ③ /SW_BAT ≥ 2 mm + /BAT_PLUS ≥ 1.5 mm con granjas de vias · ④ pares USB y ETH · ⑤ líneas de sensado · ⑥ todo lo demás.</li>
|
||||||
|
<li><b>Rellena las zonas, DRC completo</b>, y luego el punto de control de revisión externa G2 antes de ordenar.</li>
|
||||||
|
<li><b>Pendientes de banco arrastrados:</b> medir la subida de 3V3_GNSS de U21 (ventana de arranque del F9P), verificar el EP de U25 contra el dibujo DDA de TI, y el chequeo del jumper DzG1 en las tarjetas v5.5 ya fabricadas.</li>
|
||||||
|
</ol>
|
||||||
|
|
||||||
|
<p class="sub" style="margin-top:36px">EinarBoard HBOX v6 · Helgen · actualizado 05-sep-2026 · Traducción del original en inglés (<code>docs/…_EN.html</code>) — ante cualquier discrepancia, el original manda.</p>
|
||||||
|
</div>
|
||||||
79
docs/hardware/img/u25-lazo-caliente.svg
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docs/hardware/img/u25-lazo-caliente.svg
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|
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218
docs/hardware/v6-auditoria-prefab.md
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docs/hardware/v6-auditoria-prefab.md
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|
|||||||
|
---
|
||||||
|
title: HBOX v6 — Auditoría pre-fabricación y lista de trabajo
|
||||||
|
tags: [project-drogheda, hardware, hbox, v6, pcb, auditoria, jlcpcb]
|
||||||
|
project: Project Drogheda
|
||||||
|
author: Helgen Technologies
|
||||||
|
date: 2026-09-25
|
||||||
|
version: 1.0
|
||||||
|
status: ACTIVO — NO se ordena hasta cerrar la sección 3
|
||||||
|
audience: Michelle (layout), Leo
|
||||||
|
---
|
||||||
|
|
||||||
|
# HBOX v6 — Auditoría pre-fabricación
|
||||||
|
|
||||||
|
**Tarjeta:** `hbox-watchdog-v6` (repo **HBox_PCB**) · **Pedido previsto:** 5 prototipos en JLCPCB
|
||||||
|
(PCB + ensamble) · **Fecha:** 25-sep-2026 · [English version](v6-prefab-audit.md)
|
||||||
|
|
||||||
|
!!! danger "Veredicto: TODAVÍA NO se ordena"
|
||||||
|
Lo que dependía de esquemático, BOM y atributos **ya está resuelto** (sección 2).
|
||||||
|
Faltan **trabajos de layout** (sección 3, Michelle) y **tres decisiones/compras** (sección 4, Leo).
|
||||||
|
Cuando Michelle suba su trabajo, Claude repite la auditoría completa y da el **GO** final.
|
||||||
|
|
||||||
|
**Estado hoy:** DRC **0 errores**, 0 sin conectar, 0 pistas colgando · ERC **0 errores** ·
|
||||||
|
BOM: todas las piezas pobladas tienen número LCSC verificado.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 1. ¿Por qué "DRC 0" no basta?
|
||||||
|
|
||||||
|
El DRC solo compara la geometría contra las reglas de separación del propio archivo. **No ve**:
|
||||||
|
|
||||||
|
- un regulador conmutado con su diodo a 18 mm (debe estar a ≤ 4 mm),
|
||||||
|
- una pista de 0.25 mm llevando 2.5 A,
|
||||||
|
- una pieza sin número LCSC (JLC simplemente **no la coloca**),
|
||||||
|
- un chip de potencia **sin vías** bajo su pad térmico.
|
||||||
|
|
||||||
|
Eso es lo que revisó esta auditoría.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 2. Lo que YA quedó resuelto (no hay que hacer nada)
|
||||||
|
|
||||||
|
| # | Qué | Detalle |
|
||||||
|
|---|---|---|
|
||||||
|
| ✅ | **SIM: el porta-SIM físico es ahora el principal** | Telcel no dará la MFF2. **J14** (nano-SIM JAE, LCSC C2977286) + R131–R134 **se montan**; U22 (MFF2) + R127–R130 quedan **sin montar (DNP)**. La huella de la MFF2 se queda en la tarjeta como opción futura. |
|
||||||
|
| ✅ | **U19 (módem) y L22** marcados SMD | Estaban como "through-hole" y JLC los habría dejado fuera de la línea SMT. Corregido también en la librería. |
|
||||||
|
| ✅ | **64 piezas sin número LCSC** | Todas con número verificado en la base de JLC (Basic cuando se pudo). JP1–JP5 (puentes de soldadura) fuera del BOM. |
|
||||||
|
| ✅ | **Fusible de entrada F2** | Ahora es **fusible en porta-fusible**: Littelfuse **0154002.DR** (C206910), bloque SMD 9.7 × 5 mm con fusible NANO2 de 2 A / 125 V. En campo se **saca y se cambia el fusible sin soldar**. *(Falta cambiar la huella en el PCB → tarea M2.)* |
|
||||||
|
| ✅ | **Barrenos de montaje** | Los 4 en un rectángulo exacto de **130.0 × 90.0 mm**, a 5 mm de cada orilla; nombres únicos MH5–MH8. |
|
||||||
|
| ✅ | Limpieza | 6 tramos de pista colgando borrados; copias "respaldo" fuera de git; reglas de ancho de potencia en el DRC. |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 3. Lo que falta — lista de trabajo de **Michelle**
|
||||||
|
|
||||||
|
!!! warning "Antes de empezar — tres reglas"
|
||||||
|
1. **Primero `git pull`.** Claude cambió el `.kicad_pcb` hoy (atributos, LCSC, barrenos, fusible).
|
||||||
|
Si trabajas sobre una copia vieja y la guardas, se pierde todo eso.
|
||||||
|
2. **NO usar "Actualizar PCB desde esquemático"** hasta que Leo decida J10/P11/P12 (sección 4):
|
||||||
|
los volvería a poner como montados.
|
||||||
|
3. Si KiCad avisa que el archivo **cambió en disco**, elegir **Recargar**. Nunca guardar encima una copia vieja.
|
||||||
|
|
||||||
|
Orden recomendado (de mayor a menor impacto):
|
||||||
|
|
||||||
|
### M1 · Traer los cambios
|
||||||
|
|
||||||
|
- [ ] `git pull` en HBox_PCB (ver sección 6).
|
||||||
|
|
||||||
|
### M2 · Cambiar la huella de F2 (fusible)
|
||||||
|
|
||||||
|
- [ ] En el PCB: clic derecho en **F2** → *Change Footprint…* → `Fuse:Fuseholder_Littelfuse_Nano2_154x`.
|
||||||
|
- [ ] El bloque mide **9.7 × 5 mm** (antes 4.5 × 3.2). Acomodarlo cerca de donde está (159.5, 127),
|
||||||
|
entre **P1** (entrada 24 V) y **Q23**. Pistas **/24V_IN** y **/VIN_FUSED** de **≥ 1.5 mm**.
|
||||||
|
- [ ] Dejar **acceso con pinzas** al fusible (se saca hacia arriba): nada alto a menos de 2 mm de sus lados largos.
|
||||||
|
|
||||||
|
### M3 · Rehacer el grupo del regulador U25 (24 V → 5 V) — **la más importante**
|
||||||
|
|
||||||
|
**Problema:** U25 (TPS54360B) está 15 mm al norte de sus piezas de potencia:
|
||||||
|
|
||||||
|
| Medida | Hoy | Objetivo |
|
||||||
|
|---|---|---|
|
||||||
|
| Diodo **D34** (cátodo) → pin 8 (SW) de U25 | **18.2 mm** | **≤ 4 mm** |
|
||||||
|
| Capacitores de entrada **C149/C150** → pin 2 (VIN) | 5–8 mm | **≤ 3 mm** |
|
||||||
|
| Inductor **L22** (pad 1) → pin 8 | **25.9 mm** | ≤ 12 mm (L22 es grande; se acepta) |
|
||||||
|
| Cobre del nodo SW (pin 8 → D34 → L22) | pista 0.5 mm | **polígono ≥ 2 mm**, lo más corto posible |
|
||||||
|
| Vías GND bajo el pad térmico de U25 | **0** | **≥ 6** (a In1 e In2) |
|
||||||
|
| R120–R123, C155, C156 (compensación/FB/RT) | cerca | ≤ 5 mm de los pines 3–6, **lejos de SW** |
|
||||||
|
|
||||||
|
<figure markdown>
|
||||||
|
{ width="100%" }
|
||||||
|
</figure>
|
||||||
|
|
||||||
|
**Idea clave:** junto a U25 ya no hay lugar (el cargador U6 y sus piezas ocupan el noreste).
|
||||||
|
Entonces **U25 baja a donde están sus piezas grandes**, en vez de subir las piezas grandes.
|
||||||
|
|
||||||
|
Pasos:
|
||||||
|
|
||||||
|
- [ ] **Paso 1 — Sacar C151** (electrolítico 100 µF, hoy en 173.75, 123.9). Es solo reserva de
|
||||||
|
energía: funciona igual a 10–20 mm. Sugerencia: rotado 90°, centrado en ≈ **(169.5, 112)**,
|
||||||
|
el hueco que deja U25. Sigue conectado a **/VIN_PROT**.
|
||||||
|
- [ ] **Paso 2 — Poner U25 donde estaba C151**, centro aprox. **(175.5, 124.5)**, girado para que:
|
||||||
|
el **pin 8 (SW)** quede en la esquina **más cercana al cátodo de D34** (el pad sur de D34, en 182.5, 126.65),
|
||||||
|
y el **pin 2 (VIN)** mire al **oeste**.
|
||||||
|
- [ ] **Paso 3 — C149 y C150 pegados al pin 2 (VIN)**, a ≤ 3 mm, con su lado GND hacia el pad
|
||||||
|
térmico de U25. Este es el lazo que radia: **entrada → U25 → D34 → GND → entrada**. Chiquito.
|
||||||
|
- [ ] **Paso 4 — D34 se queda** donde está (182.5, 123.25). Su **ánodo (GND)** va a la misma isla de
|
||||||
|
GND que C149/C150 y el pad de U25.
|
||||||
|
- [ ] **Paso 5 — L22 se queda.** Unir pin 8 → cátodo de D34 → pad 1 de L22 (193.5, 126.9) con **un
|
||||||
|
polígono de ≥ 2 mm**. No más ancho de lo necesario (es la parte que "grita").
|
||||||
|
- [ ] **Paso 6 — Piezas chicas junto con U25:** C152 (BOOT) entre pin 1 y pin 8; R120, R121, R122, R123,
|
||||||
|
C155, C156 del lado de los pines 3–6 (**lado silencioso**). El divisor FB (R121/R122) toma el 5 V
|
||||||
|
**en los capacitores de salida** C153/C154, no en el pad del inductor.
|
||||||
|
- [ ] **Paso 7 — Tierra:** una sola isla de GND en F.Cu bajo todo el grupo, **≥ 6 vías bajo el pad
|
||||||
|
térmico de U25** y 2–3 vías junto al GND de cada capacitor y del ánodo de D34.
|
||||||
|
- [ ] **Paso 8 — /VIN_PROT** desde Q23 hasta C149/C150: **≥ 1.5 mm** (o polígono).
|
||||||
|
|
||||||
|
!!! tip "Referencia"
|
||||||
|
Es el mismo acomodo que el diseño de referencia de TI para el TPS54360 y que la
|
||||||
|
[Guía de cobre y colocación EMC v6, §2](EinarBoard-v6_Plan-de-Cobre_ES.html).
|
||||||
|
|
||||||
|
### M4 · Mismo arreglo, más chico, en el regulador del módem U20
|
||||||
|
|
||||||
|
| Medida | Hoy | Objetivo |
|
||||||
|
|---|---|---|
|
||||||
|
| L20 (pad SW) → pin 8 (SW) de U20 | 7.6 mm, pista de **23 mm** a 0.25 mm | **≤ 3 mm**, pista corta **≥ 1 mm** |
|
||||||
|
| C127 (10 µF) → pin 2 (VIN) de U20 | 5.4 mm | **≤ 3 mm** |
|
||||||
|
| Vías GND bajo el pad de U20 | 0 | **≥ 4** |
|
||||||
|
|
||||||
|
- [ ] Acercar **L20** al pin 8 de U20 y rutear **/SW_MODEM** directo y ancho.
|
||||||
|
- [ ] Acercar **C127** al pin 2. (C128 ya está bien, a 2 mm.)
|
||||||
|
- [ ] Vías bajo el pad térmico de U20.
|
||||||
|
|
||||||
|
### M5 · Vías bajo los otros chips de potencia
|
||||||
|
|
||||||
|
- [ ] **U6** (LTC4040, cargador de batería), **U2** y **U12** (MP1584): hoy **0 vías** bajo su pad
|
||||||
|
térmico. Poner **≥ 4** en cada uno (el pad térmico también es su tierra y su disipador).
|
||||||
|
|
||||||
|
### M6 · Ensanchar las pistas de potencia
|
||||||
|
|
||||||
|
Usa esta tabla (la lista de avisos del DRC está incompleta: no marca SW_BAT ni las del módem).
|
||||||
|
|
||||||
|
| Prioridad | Red | Hoy | Objetivo | Por qué |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| 1 | **/SW_BAT** | 0.25 mm, 12 mm | **≥ 1.0 mm** o polígono | ~2.5 A de batería. Ya se marcó crítica en la v5.5 (0.3 mm); en v6 está más delgada. |
|
||||||
|
| 2 | **/VEH5V** | cuello 0.25 + 0.5 mm, ~110 mm | **≥ 1.0 mm** | Salida de U25, hasta ~3 A |
|
||||||
|
| 3 | **/MAIN5V**, **/SYS5V** | 0.25–0.5 mm, 100–150 mm c/u | **≥ 1.0 mm** en el tronco | 5 V principal de toda la tarjeta |
|
||||||
|
| 4 | **/BAT_PLUS** | 0.25–0.5 mm, 118 mm | **≥ 1.0 mm** | Corriente de batería |
|
||||||
|
| 5 | **/SW_MODEM** | 0.25 mm, 23 mm | ≥ 1.0 mm **y corta** | Se resuelve con M4 |
|
||||||
|
| 6 | **/VBAT_MODEM** | cuello 0.25 (1 mm), 0.5 (11 mm) | **≥ 1.0 mm** | Picos de 2 A al transmitir |
|
||||||
|
| 7 | /VIN_MODEM, /SW_IN, /VIN_SW | 0.25–0.5 mm | ≥ 0.8 mm | Entradas de reguladores |
|
||||||
|
| — | /VIN_PROT, /SW_PWRIN | 0.5 mm | — | Se resuelven con M3 |
|
||||||
|
| No | /3V3_ETH, /5V_FAN, /SW_FAN, /FAN_RET | 0.25–0.5 mm | dejar | Menos de 0.3 A |
|
||||||
|
|
||||||
|
- [ ] Prioridades 1 a 7.
|
||||||
|
|
||||||
|
### M7 · Cerrar
|
||||||
|
|
||||||
|
- [ ] **Rellenar zonas** (tecla **B**) — los barrenos se movieron y el relleno es viejo.
|
||||||
|
- [ ] **DRC → 0 errores.** (Los avisos amarillos de ancho de pista que queden en redes "No" de la tabla están bien.)
|
||||||
|
- [ ] Revisar en el visor 3D que **J14** (porta-SIM) tenga el frente libre: la tarjeta entra por un
|
||||||
|
extremo corto; confirmar cuál en el dibujo de JAE y dejar ~6 mm libres enfrente.
|
||||||
|
- [ ] `git add` + `commit` + `push` (sección 6) y **avisar a Leo**.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 4. Lo que falta — **Leo**
|
||||||
|
|
||||||
|
- [ ] **Pre-ordenar J14** (C2977286) en la cuenta de JLC: es parte "Pre-ordered", sin eso no la colocan.
|
||||||
|
- [ ] **Decidir J10 (RJ45), P11 y P12:** ¿se montan en esta corrida? Hoy están DNP solo en el PCB.
|
||||||
|
- [ ] **Revisar las piezas donde la elección importa:** L20 Sunlord MWSA0804S-4R7MT (C17700167; checar que sus pads
|
||||||
|
entren en la huella SRU8028), L21 Murata LQG18HN68NJ00D (C162555, choke de la antena GNSS),
|
||||||
|
C149/C150 2.2 µF 100 V (C153036), C151 Nichicon 100 µF 50 V (C116241), RS1 10 mΩ 1 W (C105362),
|
||||||
|
F2 0154002.DR (C206910).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 5. Parámetros del pedido en JLCPCB (cuando haya GO)
|
||||||
|
|
||||||
|
| Opción | Valor |
|
||||||
|
|---|---|
|
||||||
|
| Capas / espesor | 4 capas, 1.6 mm, stackup **JLC04161H-7628** |
|
||||||
|
| Acabado | **ENIG** (obligatorio por los módulos LGA U19 y U18) |
|
||||||
|
| Ensamble | **Standard PCBA**, solo lado superior |
|
||||||
|
| Rayos X | Pedir en **U19** (A7670SA) y **U18** (ZED-F9P) |
|
||||||
|
| Pre-orden | **J14 C2977286** antes del pedido |
|
||||||
|
| Piezas through-hole | H4, J9, J11, K1, P1–P10, SW1, SW2 (16): soldar a mano en 5 piezas es razonable |
|
||||||
|
| Archivos | BOM/CPL generados **del PCB** (Fabrication Toolkit). Revisar rotaciones en la vista previa de JLC: U19, U18, J14, SOT-23 |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 6. Comandos de git
|
||||||
|
|
||||||
|
**Michelle** (clon de HBox_PCB):
|
||||||
|
|
||||||
|
```bash
|
||||||
|
git pull
|
||||||
|
# … trabajo en KiCad, guardar …
|
||||||
|
git add hbox-watchdog-v6.kicad_pcb
|
||||||
|
git commit -m "v6 layout: U25/U20 regrouped, thermal vias, power widths, F2 holder"
|
||||||
|
git push
|
||||||
|
```
|
||||||
|
|
||||||
|
**Leo** (proyecto Drogheda, después de que Michelle suba):
|
||||||
|
|
||||||
|
```bash
|
||||||
|
cd ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad && git pull helgen main
|
||||||
|
cd ~/Documents/Claude/Projects/Drogheda && git add 03-Architecture-Hardware/kicad && git commit -m "bump kicad" && git push
|
||||||
|
```
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 7. Historial de cambios de esta auditoría (HBox_PCB)
|
||||||
|
|
||||||
|
| Commit | Qué |
|
||||||
|
|---|---|
|
||||||
|
| `bb78cb8` · `0288bd0` | T14: J14 principal, U22 DNP, errores ERC corregidos, LCSC de J14 |
|
||||||
|
| `91d2049` · `8a49327` | T15: LCSC en 64 piezas, JP fuera del BOM, SIM + U19/L22 en el PCB, pistas colgando, avisos de ancho; librería |
|
||||||
|
| `61652cc` | T16: barrenos 130 × 90 mm, MH5–MH8 |
|
||||||
|
| `d2db77f` · `03d83d1` | T17: fusible F2 → porta-fusible 0154002.DR |
|
||||||
218
docs/hardware/v6-prefab-audit.md
Normal file
218
docs/hardware/v6-prefab-audit.md
Normal file
@ -0,0 +1,218 @@
|
|||||||
|
---
|
||||||
|
title: HBOX v6 — Pre-fabrication audit and work list
|
||||||
|
tags: [project-drogheda, hardware, hbox, v6, pcb, audit, jlcpcb]
|
||||||
|
project: Project Drogheda
|
||||||
|
author: Helgen Technologies
|
||||||
|
date: 2026-09-25
|
||||||
|
version: 1.0
|
||||||
|
status: ACTIVE — do NOT order until section 3 is closed
|
||||||
|
audience: Michelle (layout), Leo
|
||||||
|
---
|
||||||
|
|
||||||
|
# HBOX v6 — Pre-fabrication audit
|
||||||
|
|
||||||
|
**Board:** `hbox-watchdog-v6` (repo **HBox_PCB**) · **Planned order:** 5 prototypes at JLCPCB
|
||||||
|
(PCB + assembly) · **Date:** 25-Sep-2026 · [Versión en español](v6-auditoria-prefab.md)
|
||||||
|
|
||||||
|
!!! danger "Verdict: NOT ready to order yet"
|
||||||
|
Everything that depended on the schematic, BOM and attributes **is already fixed** (section 2).
|
||||||
|
What's left is **layout work** (section 3, Michelle) and **three decisions/purchases** (section 4, Leo).
|
||||||
|
When Michelle pushes her work, Claude re-runs the full audit and gives the final **GO**.
|
||||||
|
|
||||||
|
**Status today:** DRC **0 errors**, 0 unconnected, 0 dangling tracks · ERC **0 errors** ·
|
||||||
|
BOM: every populated part has a verified LCSC number.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 1. Why "DRC 0" isn't enough
|
||||||
|
|
||||||
|
DRC only compares geometry against the file's own clearance rules. It **cannot see**:
|
||||||
|
|
||||||
|
- a switching regulator with its diode 18 mm away (it must be ≤ 4 mm),
|
||||||
|
- a 0.25 mm track carrying 2.5 A,
|
||||||
|
- a part with no LCSC number (JLC simply **doesn't place it**),
|
||||||
|
- a power chip with **no vias** under its thermal pad.
|
||||||
|
|
||||||
|
That's what this audit checked.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 2. Already fixed (nothing to do)
|
||||||
|
|
||||||
|
| # | What | Detail |
|
||||||
|
|---|---|---|
|
||||||
|
| ✅ | **SIM: the physical SIM holder is now the primary SIM** | Telcel won't supply the MFF2. **J14** (JAE nano-SIM, LCSC C2977286) + R131–R134 are **fitted**; U22 (MFF2) + R127–R130 are **not fitted (DNP)**. The MFF2 footprint stays on the board as a future option. |
|
||||||
|
| ✅ | **U19 (modem) and L22** set to SMD | They were marked "through-hole", so JLC would have left them off the SMT line. Also fixed in the library. |
|
||||||
|
| ✅ | **64 parts with no LCSC number** | All given verified numbers from the JLC database (Basic where possible). JP1–JP5 (solder jumpers) removed from the BOM. |
|
||||||
|
| ✅ | **Input fuse F2** | Now a **fuse in a holder**: Littelfuse **0154002.DR** (C206910), 9.7 × 5 mm SMD block with a 2 A / 125 V NANO2 fuse. In the field the **fuse pulls out and is replaced without soldering**. *(The PCB footprint still has to be swapped → task M2.)* |
|
||||||
|
| ✅ | **Mounting holes** | All 4 on an exact **130.0 × 90.0 mm** rectangle, 5 mm from each edge; unique names MH5–MH8. |
|
||||||
|
| ✅ | Cleanup | 6 dangling track pieces deleted; "respaldo" copies out of git; power-width rules added to DRC. |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 3. What's left — **Michelle's** work list
|
||||||
|
|
||||||
|
!!! warning "Before you start — three rules"
|
||||||
|
1. **`git pull` first.** Claude changed the `.kicad_pcb` today (attributes, LCSC, holes, fuse).
|
||||||
|
If you work on an old copy and save it, all of that is lost.
|
||||||
|
2. **Do NOT use "Update PCB from Schematic"** until Leo decides J10/P11/P12 (section 4):
|
||||||
|
it would set them back to fitted.
|
||||||
|
3. If KiCad says the file **changed on disk**, choose **Reload**. Never save an old copy over it.
|
||||||
|
|
||||||
|
Recommended order (highest impact first):
|
||||||
|
|
||||||
|
### M1 · Get the changes
|
||||||
|
|
||||||
|
- [ ] `git pull` in HBox_PCB (see section 6).
|
||||||
|
|
||||||
|
### M2 · Swap the F2 (fuse) footprint
|
||||||
|
|
||||||
|
- [ ] In the PCB: right-click **F2** → *Change Footprint…* → `Fuse:Fuseholder_Littelfuse_Nano2_154x`.
|
||||||
|
- [ ] The block is **9.7 × 5 mm** (was 4.5 × 3.2). Keep it near its current spot (159.5, 127),
|
||||||
|
between **P1** (24 V input) and **Q23**. Tracks **/24V_IN** and **/VIN_FUSED** **≥ 1.5 mm**.
|
||||||
|
- [ ] Leave **tweezer access** to the fuse (it pulls straight up): nothing tall within 2 mm of its long sides.
|
||||||
|
|
||||||
|
### M3 · Rebuild the U25 regulator group (24 V → 5 V) — **the most important one**
|
||||||
|
|
||||||
|
**Problem:** U25 (TPS54360B) sits 15 mm north of its power parts:
|
||||||
|
|
||||||
|
| Measurement | Now | Target |
|
||||||
|
|---|---|---|
|
||||||
|
| Diode **D34** (cathode) → U25 pin 8 (SW) | **18.2 mm** | **≤ 4 mm** |
|
||||||
|
| Input capacitors **C149/C150** → pin 2 (VIN) | 5–8 mm | **≤ 3 mm** |
|
||||||
|
| Inductor **L22** (pad 1) → pin 8 | **25.9 mm** | ≤ 12 mm (L22 is big; acceptable) |
|
||||||
|
| SW node copper (pin 8 → D34 → L22) | 0.5 mm track | **polygon ≥ 2 mm**, as short as possible |
|
||||||
|
| GND vias under U25's thermal pad | **0** | **≥ 6** (to In1 and In2) |
|
||||||
|
| R120–R123, C155, C156 (compensation/FB/RT) | nearby | ≤ 5 mm from pins 3–6, **away from SW** |
|
||||||
|
|
||||||
|
<figure markdown>
|
||||||
|
{ width="100%" }
|
||||||
|
</figure>
|
||||||
|
|
||||||
|
**Key idea:** there's no room left around U25 (the U6 charger and its parts fill the north-east).
|
||||||
|
So **U25 moves down to its big parts**, instead of moving the big parts up.
|
||||||
|
|
||||||
|
Steps:
|
||||||
|
|
||||||
|
- [ ] **Step 1 — Move C151 out** (100 µF electrolytic, now at 173.75, 123.9). It's only an energy
|
||||||
|
reservoir and works the same 10–20 mm away. Suggestion: rotated 90°, centred at ≈ **(169.5, 112)**,
|
||||||
|
the gap U25 leaves behind. It stays on **/VIN_PROT**.
|
||||||
|
- [ ] **Step 2 — Put U25 where C151 was**, centre ≈ **(175.5, 124.5)**, rotated so that
|
||||||
|
**pin 8 (SW)** is the corner **closest to D34's cathode** (D34's south pad, at 182.5, 126.65)
|
||||||
|
and **pin 2 (VIN)** faces **west**.
|
||||||
|
- [ ] **Step 3 — C149 and C150 right against pin 2 (VIN)**, ≤ 3 mm, with their GND end toward U25's
|
||||||
|
thermal pad. This is the loop that radiates: **input → U25 → D34 → GND → input**. Keep it tiny.
|
||||||
|
- [ ] **Step 4 — D34 stays** where it is (182.5, 123.25). Its **anode (GND)** goes to the same GND
|
||||||
|
island as C149/C150 and U25's pad.
|
||||||
|
- [ ] **Step 5 — L22 stays.** Join pin 8 → D34 cathode → L22 pad 1 (193.5, 126.9) with **one polygon
|
||||||
|
≥ 2 mm wide**. No wider than needed (this is the node that "shouts").
|
||||||
|
- [ ] **Step 6 — Small parts go with U25:** C152 (BOOT) between pin 1 and pin 8; R120, R121, R122, R123,
|
||||||
|
C155, C156 on the pin 3–6 side (**quiet side**). The FB divider (R121/R122) senses 5 V **at the
|
||||||
|
output capacitors** C153/C154, not at the inductor pad.
|
||||||
|
- [ ] **Step 7 — Ground:** one GND island on F.Cu under the whole group, **≥ 6 vias under U25's thermal
|
||||||
|
pad**, and 2–3 vias next to each capacitor GND and D34's anode.
|
||||||
|
- [ ] **Step 8 — /VIN_PROT** from Q23 to C149/C150: **≥ 1.5 mm** (or a polygon).
|
||||||
|
|
||||||
|
!!! tip "Reference"
|
||||||
|
This is the same arrangement as TI's reference layout for the TPS54360 and the
|
||||||
|
[v6 Copper & EMC placement guide, §2](EinarBoard-v6_Copper-Plan_EN.html).
|
||||||
|
|
||||||
|
### M4 · Same fix, smaller, on the modem regulator U20
|
||||||
|
|
||||||
|
| Measurement | Now | Target |
|
||||||
|
|---|---|---|
|
||||||
|
| L20 (SW pad) → U20 pin 8 (SW) | 7.6 mm, **23 mm** track at 0.25 mm | **≤ 3 mm**, short track **≥ 1 mm** |
|
||||||
|
| C127 (10 µF) → U20 pin 2 (VIN) | 5.4 mm | **≤ 3 mm** |
|
||||||
|
| GND vias under U20's pad | 0 | **≥ 4** |
|
||||||
|
|
||||||
|
- [ ] Move **L20** next to U20 pin 8 and route **/SW_MODEM** short and wide.
|
||||||
|
- [ ] Move **C127** next to pin 2. (C128 is already fine, at 2 mm.)
|
||||||
|
- [ ] Vias under U20's thermal pad.
|
||||||
|
|
||||||
|
### M5 · Vias under the other power chips
|
||||||
|
|
||||||
|
- [ ] **U6** (LTC4040 battery charger), **U2** and **U12** (MP1584): **0 vias** under their thermal pad
|
||||||
|
today. Add **≥ 4** each (the thermal pad is also their ground and their heatsink).
|
||||||
|
|
||||||
|
### M6 · Widen the power tracks
|
||||||
|
|
||||||
|
Use this table (the DRC warning list is incomplete: it misses SW_BAT and the modem nets).
|
||||||
|
|
||||||
|
| Priority | Net | Now | Target | Why |
|
||||||
|
|---|---|---|---|---|
|
||||||
|
| 1 | **/SW_BAT** | 0.25 mm, 12 mm | **≥ 1.0 mm** or polygon | ~2.5 A battery path. Already flagged critical in v5.5 (0.3 mm); v6 is thinner. |
|
||||||
|
| 2 | **/VEH5V** | 0.25 neck + 0.5 mm, ~110 mm | **≥ 1.0 mm** | U25 output, up to ~3 A |
|
||||||
|
| 3 | **/MAIN5V**, **/SYS5V** | 0.25–0.5 mm, 100–150 mm each | **≥ 1.0 mm** on the trunk | Main 5 V for the whole board |
|
||||||
|
| 4 | **/BAT_PLUS** | 0.25–0.5 mm, 118 mm | **≥ 1.0 mm** | Battery current |
|
||||||
|
| 5 | **/SW_MODEM** | 0.25 mm, 23 mm | ≥ 1.0 mm **and short** | Solved by M4 |
|
||||||
|
| 6 | **/VBAT_MODEM** | 0.25 neck (1 mm), 0.5 (11 mm) | **≥ 1.0 mm** | 2 A bursts when transmitting |
|
||||||
|
| 7 | /VIN_MODEM, /SW_IN, /VIN_SW | 0.25–0.5 mm | ≥ 0.8 mm | Regulator inputs |
|
||||||
|
| — | /VIN_PROT, /SW_PWRIN | 0.5 mm | — | Solved by M3 |
|
||||||
|
| No | /3V3_ETH, /5V_FAN, /SW_FAN, /FAN_RET | 0.25–0.5 mm | leave | Under 0.3 A |
|
||||||
|
|
||||||
|
- [ ] Priorities 1 to 7.
|
||||||
|
|
||||||
|
### M7 · Close out
|
||||||
|
|
||||||
|
- [ ] **Refill zones** (key **B**) — the holes moved and the fill is stale.
|
||||||
|
- [ ] **DRC → 0 errors.** (Yellow track-width warnings left on the "No" nets in the table are fine.)
|
||||||
|
- [ ] Check in the 3D viewer that **J14** (SIM holder) has a clear front: the card enters from one
|
||||||
|
short end; confirm which on the JAE drawing and leave ~6 mm clear in front of it.
|
||||||
|
- [ ] `git add` + `commit` + `push` (section 6) and **tell Leo**.
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 4. What's left — **Leo**
|
||||||
|
|
||||||
|
- [ ] **Pre-order J14** (C2977286) into the JLC account: it's a "Pre-ordered" part; they won't place it otherwise.
|
||||||
|
- [ ] **Decide J10 (RJ45), P11 and P12:** fitted on this run? Today they're DNP on the PCB only.
|
||||||
|
- [ ] **Review the parts where the choice matters:** L20 Sunlord MWSA0804S-4R7MT (C17700167; check its pads fit the
|
||||||
|
SRU8028 footprint), L21 Murata LQG18HN68NJ00D (C162555, GNSS antenna choke),
|
||||||
|
C149/C150 2.2 µF 100 V (C153036), C151 Nichicon 100 µF 50 V (C116241), RS1 10 mΩ 1 W (C105362),
|
||||||
|
F2 0154002.DR (C206910).
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 5. JLCPCB order settings (once it's GO)
|
||||||
|
|
||||||
|
| Option | Value |
|
||||||
|
|---|---|
|
||||||
|
| Layers / thickness | 4 layers, 1.6 mm, stackup **JLC04161H-7628** |
|
||||||
|
| Finish | **ENIG** (required for the LGA modules U19 and U18) |
|
||||||
|
| Assembly | **Standard PCBA**, top side only |
|
||||||
|
| X-ray | Request on **U19** (A7670SA) and **U18** (ZED-F9P) |
|
||||||
|
| Pre-order | **J14 C2977286** before the order |
|
||||||
|
| Through-hole parts | H4, J9, J11, K1, P1–P10, SW1, SW2 (16): hand-soldering on 5 boards is reasonable |
|
||||||
|
| Files | BOM/CPL generated **from the PCB** (Fabrication Toolkit). Check rotations in JLC's preview: U19, U18, J14, SOT-23s |
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 6. Git commands
|
||||||
|
|
||||||
|
**Michelle** (HBox_PCB clone):
|
||||||
|
|
||||||
|
```bash
|
||||||
|
git pull
|
||||||
|
# … work in KiCad, save …
|
||||||
|
git add hbox-watchdog-v6.kicad_pcb
|
||||||
|
git commit -m "v6 layout: U25/U20 regrouped, thermal vias, power widths, F2 holder"
|
||||||
|
git push
|
||||||
|
```
|
||||||
|
|
||||||
|
**Leo** (Drogheda project, after Michelle pushes):
|
||||||
|
|
||||||
|
```bash
|
||||||
|
cd ~/Documents/Claude/Projects/Drogheda/03-Architecture-Hardware/kicad && git pull helgen main
|
||||||
|
cd ~/Documents/Claude/Projects/Drogheda && git add 03-Architecture-Hardware/kicad && git commit -m "bump kicad" && git push
|
||||||
|
```
|
||||||
|
|
||||||
|
---
|
||||||
|
|
||||||
|
## 7. Change history for this audit (HBox_PCB)
|
||||||
|
|
||||||
|
| Commit | What |
|
||||||
|
|---|---|
|
||||||
|
| `bb78cb8` · `0288bd0` | T14: J14 primary, U22 DNP, ERC errors fixed, J14 LCSC |
|
||||||
|
| `91d2049` · `8a49327` | T15: LCSC on 64 parts, JP out of BOM, SIM + U19/L22 on the PCB, dangling tracks, width warnings; library |
|
||||||
|
| `61652cc` | T16: holes 130 × 90 mm, MH5–MH8 |
|
||||||
|
| `d2db77f` · `03d83d1` | T17: fuse F2 → 0154002.DR holder |
|
||||||
@ -66,6 +66,12 @@ nav:
|
|||||||
- "4 · Prueba final antes de embarcar": procedimientos/v5-prueba-final-unidad.md
|
- "4 · Prueba final antes de embarcar": procedimientos/v5-prueba-final-unidad.md
|
||||||
- "Tablero de producción": tablero.html
|
- "Tablero de producción": tablero.html
|
||||||
|
|
||||||
|
- "🛠 Hardware v6 — fabricación":
|
||||||
|
- "Auditoría pre-fabricación (español)": hardware/v6-auditoria-prefab.md
|
||||||
|
- "Pre-fabrication audit (English)": hardware/v6-prefab-audit.md
|
||||||
|
- "Plan de cobre y colocación EMC (ES)": hardware/EinarBoard-v6_Plan-de-Cobre_ES.html
|
||||||
|
- "Copper plan & EMC placement (EN)": hardware/EinarBoard-v6_Copper-Plan_EN.html
|
||||||
|
|
||||||
- "🔩 Montaje y arneses":
|
- "🔩 Montaje y arneses":
|
||||||
- "Pinout de arneses y conectores": montaje/pinout-arneses.md
|
- "Pinout de arneses y conectores": montaje/pinout-arneses.md
|
||||||
- "BOM dividido para ensamble": montaje/bom-split.md
|
- "BOM dividido para ensamble": montaje/bom-split.md
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user