7dd67e5129
kicad: V5.6 ECO schematic
2026-09-28 14:24:57 -06:00
f0cfc9fa68
auto-sync 2026-09-27 18:00
2026-09-27 18:00:14 -06:00
966c84d395
auto-sync 2026-09-26 18:00
2026-09-26 18:00:15 -06:00
c734e8061d
v6 T17b script + bump kicad (F2 fuse holder)
...
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 20:27:59 +00:00
d46b81baf5
v6 T17 script + bump kicad (F2 fuse)
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 20:24:31 +00:00
c160ed4aa6
v6 T16 script + bump kicad (mounting holes 130 x 90)
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 19:53:56 +00:00
2b03a7ee02
bump kicad: audit status after T15
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 19:00:26 +00:00
cb244f25bf
bump kicad: SMD attr fix in Drogheda-v6 lib
...
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 18:59:46 +00:00
9367527d85
v6 T15/T15b scripts + bump kicad (JLC BOM, board attrs, stubs)
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 18:59:26 +00:00
3014b92f08
bump kicad: v6 pre-fab audit report
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 18:40:50 +00:00
31d0e43a7f
v6 T14b: J14 LCSC + bump kicad
...
T14 script extended (idempotent): J14 gets LCSC C2977286 and a primary-SIM
description. ERC 0 errors.
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 18:37:54 +00:00
90835738a6
v6 T14 script + bump kicad (SIM holder primary, ERC 0; also picks up 021708b silkscreen)
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Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-25 18:34:09 +00:00
985a2daa6e
kicad: bump al tablero con DRC 0 del ingeniero
2026-09-25 12:00:56 -06:00
d3b72835ad
auto-sync 2026-09-24 18:00
2026-09-24 18:00:15 -06:00
d3ab138dc6
auto-sync 2026-09-19 18:00
2026-09-19 18:00:14 -06:00
2a7e5511c0
auto-sync 2026-09-18 18:00
2026-09-18 18:00:13 -06:00
63bf5cc82f
pin fw 0.5.1 + docs; htracker patch for Gibran
2026-09-18 13:12:09 -06:00
e2bf432a32
pin fw 0.5.0 + hbox-docs; prueba final de unidad
2026-09-18 11:51:14 -06:00
94ad3fad02
bump hbox-docs: diagnostico campo y banco
2026-09-18 11:28:08 -06:00
6b943e9b52
pin hbox-docs + fw at bring-up 0.2.1; procedimientos a 0.2.1
2026-09-17 18:58:48 -06:00
3c3097f0e1
06-Testing: procedimientos v5 modulos/integracion y ensamble; prueba-y-flasheo -> fw 0.2.0
2026-09-17 11:00:25 -06:00
fec3762e43
hbox-docs: actas de modulos/integracion/ensamble + fw 0.2.0
2026-09-17 10:56:12 -06:00
047ce54ade
T13 + kicad pointer
2026-09-17 10:11:32 -06:00
383bb28163
bump kicad pointer to Michelle's routing
2026-09-17 09:25:18 -06:00
12bd7afd74
bump kicad + firmware submodule pointers
2026-09-16 16:11:50 -06:00
973dbe0dad
hbox-docs: actas de prueba V5/V4 + checklist de ensamble + backend -> 57f6733
...
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-16 18:05:29 +00:00
8ea4bbc52f
v5: procedimiento de prueba y flasheo por tarjeta (lote 15 pzas, ES)
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Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-15 18:23:54 +00:00
1d06118616
hbox-docs: nuevo submodulo — sitio de documentacion para tecnicos
...
MkDocs Material (ES) con el subconjunto curado de procedimientos de banco,
montaje, diagnostico y guias git; deploy privado al servidor Helgen
(nginx + htpasswd). Repo: Helgen-Services/hbox-docs -> 01dc30c
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-15 18:23:40 +00:00
33b62d7052
Drogheda: T12 (MFF2 repoint as a replayable script) + kicad submodule bump
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scripts/2026-09-15_v6_T12_sim_dual_footprint.py moves the U22 edits into the
T-script chain. Idempotent, dry-run by default, .T12bak backups, UUID invariant
guard, and a gate-0 assertion on the MFF2 land pattern. Verified to reproduce the
hand edits byte-for-byte. Part 2 (nano-SIM holder + 0R selects) pending the
holder datasheet.
2026-09-15 10:58:36 -06:00
564c3e450d
auto-sync 2026-09-10 18:00
2026-09-10 18:00:14 -06:00
b877f0458c
auto-sync 2026-09-09 18:00
2026-09-09 18:00:15 -06:00
768f49a860
gitmodules: kicad submodule now points at Helgen server (HBox_PCB)
...
ssh://git@git.helgen.online:222/Helgen-Services/HBox_PCB.git replaces the
GitHub mirror URL, matching the external-collaborator guide. Outer repo
gains a 'helgen' remote (Helgen-Services/Drogheda.git).
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-07 18:47:32 +00:00
7f7a3d5d39
kicad submodule: C123 placement fix -> 47d1a1e
...
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-07 16:55:54 +00:00
61e10d8145
kicad submodule: external docs (git guide + Copper Plan EN/ES) -> 1a99fb3
...
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-07 16:47:21 +00:00
cb93840518
v6 Copper Plan: U18 V_BCKP (pin 36) decoupling fix
...
- pin 36 is V_BCKP on /3V3 (always-on), deliberately not /3V3_GNSS:
RTC + ephemeris survive when U21's switched rail is off
- no /3V3 cap existed within 19 mm of the pin; spare Cu4 (100nF,
already /3V3-GND) reassigned to sit at pin 36
- C123 clarified: U18 has only two VCC pins; C123 is the U21-output
third 100nF, not a VCC-pin cap
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-05 01:11:02 +00:00
5e2dc775d7
v6 Copper Plan: add master proximity table (§8)
...
- every discrete mapped to its owner designator with distance class
(glued <=3mm / close <=5mm / block <=15mm), computed from the live
netlist + hand curation (ESD at connectors, ADC filters at MCU,
comp caps at their regulator, DB1-4 -> U13, C106-108 -> U16 VDD)
- designators added to existing per-block tables (Leo's request)
- sch<->pcb designator audit: P1-P12 in sync, 0 value mismatches,
only expected diffs (U22 fp TBD, MH5/6 board-only, PF* ERC flags)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-04 01:08:49 +00:00
538b62b72c
v6 connector renumber (submodule b007c7c) + Copper Plan map
...
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-04 00:53:32 +00:00
94da1ad0eb
v6 silkscreen + gravity placement (submodule)
2026-09-03 23:50:25 +00:00
c3af7afd9c
v6 cluster placement (submodule c7d2552) + Copper Plan update
...
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-03 16:50:09 +00:00
230c1d5a2c
v6 NTC2/PA7 fix (submodule ba70f62) + Copper Plan placement/EMC guide
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Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-03 00:00:54 +00:00
53021a296a
v6 PCB copper wipe for re-layout
2026-09-02 22:59:32 +00:00
1044e706e5
auto-sync 2026-09-01 18:00
2026-09-01 18:00:17 -06:00
0a50ff7d21
v6 T11 accelerometer (submodule 23ed361) + T11 script
...
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-09-01 22:06:21 +00:00
7fea0a5c11
v6 T10 sensor set (submodule 83ed72e) + T10 script
2026-08-31 21:48:32 +00:00
0823de6c29
v6 T9 power input (submodule b92a187) + T9 script
2026-08-31 21:09:09 +00:00
a29f65d953
v6 PCB dead-copper cleanup (submodule ab2e67a)
2026-08-31 18:14:25 +00:00
5bb2e12668
kicad → submodule (hbox-kicad)
...
03-Architecture-Hardware/kicad is now its own repository so it can live on
GitHub and be pull-mirrored to the Gitea instance (Helgen-Services/HBox_PCB
on git.helgen.online).
History was extracted with:
git subtree split --prefix=03-Architecture-Hardware/kicad
so all 70 board commits survive in the submodule, with new hashes.
Parent history is untouched; tag pre-kicad-submodule-2026-08-26 marks the
state before this change.
2026-08-27 20:57:37 +00:00
Claude (Cowork)
daafd5c440
v6 T4 sync: Leo Update-PCB-from-Schematic - LTE island on the board (275 footprints)
...
All pad->net checks pass: VBAT 55/56/57 + bulk + TVS, OR-diodes into U20, RTCM path
through U24 with DNP bypasses, PWRKEY/RST FETs, SIM ESD, TP8. U22 skipped as expected
(MFF2 footprint TBD). LED re-drive verified on copper: Rmled1.1 -> /3V3, D4G1.1 ->
/MODEM_LED_K -> Q22.3.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-27 20:55:14 +00:00
Claude (Cowork)
4b8bdf4916
v6 T4c: ERC fixes - RF_IN retyped passive, PF18 PWR_FLAG on SIM_VDD
...
Leo's ERC flagged exactly two errors after the T4 sync:
1. U18 pin 2 RF_IN [Input] undriven - my hand-built ZED-F9P symbol typed the RF port as a
logic input. RF ports are conventionally passive; retyped in Drogheda-sym AND the
schematic's lib_symbols cache (1 substitution each, asserted). Its real connection
arrives with the Block S bias tee in T6.
2. U22 pin 1 VCC [Power input] undriven - SIM_VDD is fed by the modem's USIM1_VDD, whose
EasyEDA pin type is not a power output. Idiomatic fix: PF18 PWR_FLAG on SIM_VDD,
consistent with PF1-PF17.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-25 22:27:42 +00:00
Claude (Cowork)
4f6e1bb347
v6 T4: Blocks O+P+Q+R - A7670SA LTE island complete in the schematic (33/33 net checks pass)
...
Block O (modem): U19 A7670SA-LASC (C18548276, LGA-124) - 19 signal nets + 39 GND + 66 NC,
all 124 pads accounted for. UART via 1.8V-side nets (_M suffix); USB joins J9 directly
(VBUS A4/A9/B4/B9 + DP/DM); USB_BOOT -> TP8; VDD_EXT -> 1V8_MODEM (shifter reference only);
NETLIGHT (1.8V) -> R109 4.7k -> Q22 MMBT3904 low-side, reusing the existing Rmled1+D4G1 LED
string re-driven: MODEM_LED label -> 3V3, D4G1 cathode GND label -> MODEM_LED_K.
Block P (3.8V rail): 24V -> D20 SS34 || MAIN5V -> D21 PMEG3050EP (C50603) -> VIN_MODEM ->
U20 AP64350SP-13 (C2071691, 40V/3.5A) -> L20 4.7uH -> VBAT_MODEM. Values from datasheet
DS41976: FB 0.8V (R110 75k / R111 20k = 3.8V), RT R117 200k = 500kHz (pin must not float),
COMP R116 14k + C141 3.3nF + C142 47pF, BST C129 100nF, EP -> GND. EN = MODEM_PWR_EN (PC10)
with R113 100k pull-down: rail DEFAULTS OFF (invariant #1 ); EN low >= 2s = HARD_CYCLE
(invariant #3 ). Bulk: 2x 220uF/10V (C2827940) + 22uF/1uF/100nF/33pF/10pF + R112 1k bleed +
D22 SMAJ5.0A TVS (C113952). VERIFY at layout: D22 pad-1-is-cathode against the fp marker.
Block Q (SIM): U22 MFF2_SIM symbol (new in Drogheda-sym; FOOTPRINT TBD "Drogheda:MFF2_5x6_TBD"
- build from the chosen carrier chip datasheet; PCB sync will flag it, expected). SIM_VDD
100nF + PESD5V0S1BA on DATA/CLK/RST (D23-25, C2827694, orientation cloned from D14).
Block R (level shift): 2x 74LVC2T45DC (C730237, direction-fixed). U23 DIR=GND: 3V3 DIN_4G ->
1.8V DIN_4G_M. U24 DIR=1V8: DOUT_4G_M -> DOUT_4G (also feeds U18 RXD2) and MODEM_STATUS_M ->
MODEM_STATUS (PC9). R106 100R taps DOUT_4G -> USART6_RX (PC7). DNP 0R bypasses R107/R108
across the RTCM path. Q20/Q21 2N7002 open-drain on PWRKEY/RESET with 100k pull-downs -
MCU absent leaves the modem free (invariant #1 ). PWRKEY timing: SIMCom >=50ms on / >=2.5s off.
CORRECTIONS this pass: (1) the schematic has 382 WIRE SEGMENTS - the earlier "zero wires"
finding was a regex artifact (multi-line xy); label-on-pin work was unaffected (all verified
against the PCB), but the LED relabel needed a wire-graph trace, now in the script.
(2) 9 stale no_connect markers removed from MCU pins that now carry labels (PC1-PC3, PA7,
PC8-PC12). (3) A7670SA is a 124-pad LGA, not the 88 claimed in the modem survey.
NEXT: Leo runs ERC + Update PCB from Schematic (U22 will complain - footprint TBD, skip it),
then T5 = LTC4040 input-limit errata fix + U7/L7 disposition, T6 = RF Block S + netclasses.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
2026-08-25 22:20:39 +00:00
