MkDocs Material (ES) con el subconjunto curado de procedimientos de banco,
montaje, diagnostico y guias git; deploy privado al servidor Helgen
(nginx + htpasswd). Repo: Helgen-Services/hbox-docs -> 01dc30c
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
scripts/2026-09-15_v6_T12_sim_dual_footprint.py moves the U22 edits into the
T-script chain. Idempotent, dry-run by default, .T12bak backups, UUID invariant
guard, and a gate-0 assertion on the MFF2 land pattern. Verified to reproduce the
hand edits byte-for-byte. Part 2 (nano-SIM holder + 0R selects) pending the
holder datasheet.
- pin 36 is V_BCKP on /3V3 (always-on), deliberately not /3V3_GNSS:
RTC + ephemeris survive when U21's switched rail is off
- no /3V3 cap existed within 19 mm of the pin; spare Cu4 (100nF,
already /3V3-GND) reassigned to sit at pin 36
- C123 clarified: U18 has only two VCC pins; C123 is the U21-output
third 100nF, not a VCC-pin cap
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
- every discrete mapped to its owner designator with distance class
(glued <=3mm / close <=5mm / block <=15mm), computed from the live
netlist + hand curation (ESD at connectors, ADC filters at MCU,
comp caps at their regulator, DB1-4 -> U13, C106-108 -> U16 VDD)
- designators added to existing per-block tables (Leo's request)
- sch<->pcb designator audit: P1-P12 in sync, 0 value mismatches,
only expected diffs (U22 fp TBD, MH5/6 board-only, PF* ERC flags)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
03-Architecture-Hardware/kicad is now its own repository so it can live on
GitHub and be pull-mirrored to the Gitea instance (Helgen-Services/HBox_PCB
on git.helgen.online).
History was extracted with:
git subtree split --prefix=03-Architecture-Hardware/kicad
so all 70 board commits survive in the submodule, with new hashes.
Parent history is untouched; tag pre-kicad-submodule-2026-08-26 marks the
state before this change.
Leo's ERC flagged exactly two errors after the T4 sync:
1. U18 pin 2 RF_IN [Input] undriven - my hand-built ZED-F9P symbol typed the RF port as a
logic input. RF ports are conventionally passive; retyped in Drogheda-sym AND the
schematic's lib_symbols cache (1 substitution each, asserted). Its real connection
arrives with the Block S bias tee in T6.
2. U22 pin 1 VCC [Power input] undriven - SIM_VDD is fed by the modem's USIM1_VDD, whose
EasyEDA pin type is not a power output. Idiomatic fix: PF18 PWR_FLAG on SIM_VDD,
consistent with PF1-PF17.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
Leo generated the vendor part with easyeda2kicad (C5120257) -> Drogheda-v6.kicad_sym /
.pretty / .3dshapes, now registered in sym-lib-table and fp-lib-table.
CROSS-CHECK: the EasyEDA/LCSC symbol independently CONFIRMS the datasheet transcription -
pads 1-54 match the u-blox pin assignment function for function, and the 21 Reserved pads
are identical. Pads 55-102 are 48 extra GND pads (the ground array under the module), which
our symbol was missing; T3a2 adds them stacked on the pin-1 coordinate so one GND label
serves all. Symbol is now 102/102 pins, footprint = Drogheda-v6:LCC-LGA-102_L22.0-W17.0_FM660.
Block N as wired (verified by rebuilding connectivity from label-on-pin geometry):
GNSS_TX U16.16 + U18.43 GNSS_RX U16.17 + U18.42
DOUT_4G U18.26 (RXD2, RTCM in - modem end lands in T4)
USART1_RX U16.43 + Rdfu1.1 + U18.27 (TXD2 uplink; K1.1 also on this net per the PCB)
GNSS_RESET_N U16.53 (PC12) + U18.49 + R105 10k pull-up to 3V3_GNSS
GNSS_TIMEPULSE U16.23 (PA7) + U18.53
GNSS_ANT_DETECT U16.9 (PC1) + U18.4
GNSS_ANT_SHORT_N U16.10 (PC2) + U18.6
GNSS_RTK_STAT U16.11 (PC3) + U18.20 <- hardware answer to are-corrections-being-used
3V3_GNSS = U21.5 + U18.33/34 + C120-C124 + R105; U21 fed from SW_5V (stays MCU-gated)
V_BCKP = U18.36 on the UNGATED 3V3 so ephemeris survives a power-cycle
33 no-connects: the 21 reserved pads plus V_USB, USB_DM/DP, ANT_OFF, SDA, SCL, TX_READY,
D_SEL (open = UART mode), SAFEBOOT_N, EXTINT, GEOFENCE_STAT and the LDO NC/NR pin.
T3c fixes two coordinates the generators emitted as 3.552713679e-15 (i.e. zero); KiCad is
not guaranteed to accept exponent notation. See the script header for the lesson: a first
attempt used a bare numeric regex over the whole file and corrupted 264 UUIDs, because
segments such as 895e-4153 parse as scientific notation. Reverted from backup and redone
scoped to (at ...) forms only, with a UUID-integrity guard. Verified 2298 UUIDs, 0
malformed, 0 exponent coordinates.
STILL OPEN: the PCB has no U18/U21/passive footprints yet - that is a KiCad
Update-PCB-from-Schematic. And confirm the -04B datasheet pin assignment on paper.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
ZED-F9P: all 54 pins, numbers 1-54 complete and unique, transcribed from the u-blox
datasheet Table 11 (ZED-F9P-15B_DataSheet_UBX-23009090). Left column = power/RF/antenna
(17), right = interfaces/control/status (16), bottom = the 21 reserved pins. Body 55.88 x
50.8 mm. LCSC C5120257 carried as a property.
FINDING that changes Block N: the ZED-F9P HAS hardware status outputs - RTK_STAT (pin 20)
and GEOFENCE_STAT (pin 19). RTK_STAT: 0 = RTK fixed, blinking = receiving and using
corrections, 1 = no corrections. That is a HARDWARE answer to the question the June and
10-Ago RCAs could not answer. Wire RTK_STAT to PC3. (Earlier note implying only the UM980
had such pins was wrong.) ANT_OFF (pin 5) also exists.
LDO_SOT23-5: generic AP2112K / TPS7A20 pinout (1=VIN 2=GND 3=EN 4=NC/NR 5=VOUT) so U21
can be any SOT-23-5 low-noise LDO without a symbol change.
OPEN - blocks the PCB side of T3, not the schematic:
* No ZED-F9P FOOTPRINT exists. Not in the project libs, not derivable from the datasheet
(no land pattern) and the integration manual's drawings do not survive PDF text
extraction. EasyEDA/LCSC is blocked by the egress allowlist from here.
Fix: run locally -> pip install easyeda2kicad && easyeda2kicad --full --lcsc_id=C5120257
* PRE-FAB CHECK: confirm the -04B datasheet carries the SAME pin assignment as the -15B.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
Leo's post-fork V5 work was copper-only: GND stitching +4 seg/+2 vias, /SYS5V -2 seg,
zones refilled 45 -> 48 polys. No footprints added/removed/moved, no pad-net changes,
schematic byte-identical. Rather than hand-merge a routing delta, v6 was re-forked from
the new v5 and the T1/T2 generator scripts replayed - deterministic and re-runnable.
Verified v6 vs v5: GND 212 seg / 176 vias, /SYS5V 57 seg, 48 filled polys all identical;
footprints 228 -> 224 (MOD1/J7/J8/SW4G1 gone); segments 1980 -> 1974 and vias 321 -> 320
(the 7 ripped /USART1_TX items). Net assertions all pass:
/USART6_TX = U16.37 + K1.10 | /USART6_RX = U16.38 | /USART1_RX = U16.43 + Rdfu1.1 + K1.1
/DIN_4G = K1.5 + K1.6 | /USART1_TX, /DOUT_4G, /MODEM_RST retired until T3/T4.
KNOWN: v6 zone fills are inherited from v5 and still carry cutouts for the 4 deleted
footprints - needs a GUI refill (MCP refill segfaults). Cosmetic until the layout phase.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
