- every discrete mapped to its owner designator with distance class
(glued <=3mm / close <=5mm / block <=15mm), computed from the live
netlist + hand curation (ESD at connectors, ADC filters at MCU,
comp caps at their regulator, DB1-4 -> U13, C106-108 -> U16 VDD)
- designators added to existing per-block tables (Leo's request)
- sch<->pcb designator audit: P1-P12 in sync, 0 value mismatches,
only expected diffs (U22 fp TBD, MH5/6 board-only, PF* ERC flags)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
03-Architecture-Hardware/kicad is now its own repository so it can live on
GitHub and be pull-mirrored to the Gitea instance (Helgen-Services/HBox_PCB
on git.helgen.online).
History was extracted with:
git subtree split --prefix=03-Architecture-Hardware/kicad
so all 70 board commits survive in the submodule, with new hashes.
Parent history is untouched; tag pre-kicad-submodule-2026-08-26 marks the
state before this change.
Leo's ERC flagged exactly two errors after the T4 sync:
1. U18 pin 2 RF_IN [Input] undriven - my hand-built ZED-F9P symbol typed the RF port as a
logic input. RF ports are conventionally passive; retyped in Drogheda-sym AND the
schematic's lib_symbols cache (1 substitution each, asserted). Its real connection
arrives with the Block S bias tee in T6.
2. U22 pin 1 VCC [Power input] undriven - SIM_VDD is fed by the modem's USIM1_VDD, whose
EasyEDA pin type is not a power output. Idiomatic fix: PF18 PWR_FLAG on SIM_VDD,
consistent with PF1-PF17.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
Leo generated the vendor part with easyeda2kicad (C5120257) -> Drogheda-v6.kicad_sym /
.pretty / .3dshapes, now registered in sym-lib-table and fp-lib-table.
CROSS-CHECK: the EasyEDA/LCSC symbol independently CONFIRMS the datasheet transcription -
pads 1-54 match the u-blox pin assignment function for function, and the 21 Reserved pads
are identical. Pads 55-102 are 48 extra GND pads (the ground array under the module), which
our symbol was missing; T3a2 adds them stacked on the pin-1 coordinate so one GND label
serves all. Symbol is now 102/102 pins, footprint = Drogheda-v6:LCC-LGA-102_L22.0-W17.0_FM660.
Block N as wired (verified by rebuilding connectivity from label-on-pin geometry):
GNSS_TX U16.16 + U18.43 GNSS_RX U16.17 + U18.42
DOUT_4G U18.26 (RXD2, RTCM in - modem end lands in T4)
USART1_RX U16.43 + Rdfu1.1 + U18.27 (TXD2 uplink; K1.1 also on this net per the PCB)
GNSS_RESET_N U16.53 (PC12) + U18.49 + R105 10k pull-up to 3V3_GNSS
GNSS_TIMEPULSE U16.23 (PA7) + U18.53
GNSS_ANT_DETECT U16.9 (PC1) + U18.4
GNSS_ANT_SHORT_N U16.10 (PC2) + U18.6
GNSS_RTK_STAT U16.11 (PC3) + U18.20 <- hardware answer to are-corrections-being-used
3V3_GNSS = U21.5 + U18.33/34 + C120-C124 + R105; U21 fed from SW_5V (stays MCU-gated)
V_BCKP = U18.36 on the UNGATED 3V3 so ephemeris survives a power-cycle
33 no-connects: the 21 reserved pads plus V_USB, USB_DM/DP, ANT_OFF, SDA, SCL, TX_READY,
D_SEL (open = UART mode), SAFEBOOT_N, EXTINT, GEOFENCE_STAT and the LDO NC/NR pin.
T3c fixes two coordinates the generators emitted as 3.552713679e-15 (i.e. zero); KiCad is
not guaranteed to accept exponent notation. See the script header for the lesson: a first
attempt used a bare numeric regex over the whole file and corrupted 264 UUIDs, because
segments such as 895e-4153 parse as scientific notation. Reverted from backup and redone
scoped to (at ...) forms only, with a UUID-integrity guard. Verified 2298 UUIDs, 0
malformed, 0 exponent coordinates.
STILL OPEN: the PCB has no U18/U21/passive footprints yet - that is a KiCad
Update-PCB-from-Schematic. And confirm the -04B datasheet pin assignment on paper.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
ZED-F9P: all 54 pins, numbers 1-54 complete and unique, transcribed from the u-blox
datasheet Table 11 (ZED-F9P-15B_DataSheet_UBX-23009090). Left column = power/RF/antenna
(17), right = interfaces/control/status (16), bottom = the 21 reserved pins. Body 55.88 x
50.8 mm. LCSC C5120257 carried as a property.
FINDING that changes Block N: the ZED-F9P HAS hardware status outputs - RTK_STAT (pin 20)
and GEOFENCE_STAT (pin 19). RTK_STAT: 0 = RTK fixed, blinking = receiving and using
corrections, 1 = no corrections. That is a HARDWARE answer to the question the June and
10-Ago RCAs could not answer. Wire RTK_STAT to PC3. (Earlier note implying only the UM980
had such pins was wrong.) ANT_OFF (pin 5) also exists.
LDO_SOT23-5: generic AP2112K / TPS7A20 pinout (1=VIN 2=GND 3=EN 4=NC/NR 5=VOUT) so U21
can be any SOT-23-5 low-noise LDO without a symbol change.
OPEN - blocks the PCB side of T3, not the schematic:
* No ZED-F9P FOOTPRINT exists. Not in the project libs, not derivable from the datasheet
(no land pattern) and the integration manual's drawings do not survive PDF text
extraction. EasyEDA/LCSC is blocked by the egress allowlist from here.
Fix: run locally -> pip install easyeda2kicad && easyeda2kicad --full --lcsc_id=C5120257
* PRE-FAB CHECK: confirm the -04B datasheet carries the SAME pin assignment as the -15B.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
Leo's post-fork V5 work was copper-only: GND stitching +4 seg/+2 vias, /SYS5V -2 seg,
zones refilled 45 -> 48 polys. No footprints added/removed/moved, no pad-net changes,
schematic byte-identical. Rather than hand-merge a routing delta, v6 was re-forked from
the new v5 and the T1/T2 generator scripts replayed - deterministic and re-runnable.
Verified v6 vs v5: GND 212 seg / 176 vias, /SYS5V 57 seg, 48 filled polys all identical;
footprints 228 -> 224 (MOD1/J7/J8/SW4G1 gone); segments 1980 -> 1974 and vias 321 -> 320
(the 7 ripped /USART1_TX items). Net assertions all pass:
/USART6_TX = U16.37 + K1.10 | /USART6_RX = U16.38 | /USART1_RX = U16.43 + Rdfu1.1 + K1.1
/DIN_4G = K1.5 + K1.6 | /USART1_TX, /DOUT_4G, /MODEM_RST retired until T3/T4.
KNOWN: v6 zone fills are inherited from v5 and still carry cutouts for the 4 deleted
footprints - needs a GUI refill (MCP refill segfaults). Cosmetic until the layout phase.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
No footprints added, removed, moved or rotated; no pad-net changes; schematic untouched.
Captured before re-forking v6 so the v6 PCB inherits this work byte-for-byte.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
T0 hbox-watchdog-v6.{sch,pcb,pro,dru} forked from v5.5 @ e6ac8cc (new files on main,
same precedent as v4 -> v5). All internal project refs renamed, paren-balanced.
T1 Deleted the simpleRTK2B Pro socket (MOD1), both XBee sockets (J7/J8) and the modem
reset button (SW4G1) from schematic and PCB, plus the 25 on-pin labels that carried
their connectivity. The schematic has ZERO wires - connectivity is labels on pins -
so no wire/junction surgery was needed.
T2 Relay K1 pin 10 (NO contact) moves from PA9 /USART1_TX to PC6 /USART6_TX, giving the
MCU ownership of the modem RX line while K1 de-energised still feeds the receiver's
GGA straight to the modem (MCU-dead fail-safe). PA9 freed -> no_connect. USART6_RX
added on PC7. Retired /USART1_TX copper ripped (7 items).
Verified: /USART6_TX = U16.37 + K1.10 | /USART1_RX = U16.43 + Rdfu1.1 + K1.1 | PA9 free.
Nets awaiting T3/T4 silicon: /DOUT_4G, /MODEM_RST, /GNSS_TX, /GNSS_RX, /USART6_RX.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01YJ4eAB6zjQT49RVwpgfKdt
Fabrication Toolkit export of hbox-watchdog-v4 (EinarBoard 2.0), verified
before ordering. Board is 155.00 x 100.00 mm, 4 layers, 1.6 mm.
New in production/:
HBOX_v4_PROD.zip 15 gerber + drill files
HBOX_v4_PROD_bom.csv 102 lines, 25 with an LCSC number
HBOX_v4_PROD_positions.csv 187 rows
HBOX_v4_PROD_designators.csv toolkit by-product, not a JLC input
hbox-watchdog-v4.kicad_pcb is modified only because the toolkit's AUTO FILL
refilled zones and re-saved on export. Diffed before/after: 0 footprints
moved, 0 rotated, 0 changed side; tracks 1989 -> 1989, vias 351 -> 351,
zones 5 -> 5, filled polygons 41 -> 41. Zone fill data only.
Verification (details in the order walkthrough):
- Row counts matched a prediction registered before the export existed:
CPL 187, BOM 102, 35 machine-placed. No duplicate designators, no
collisions from the toolkit's uppercasing of refdes, nothing truncated.
- All 30 pre-registered rotation predictions matched exactly, 0 mismatches.
The five previously-unproven packages resolved as J10 +0 deg and
U10/U11/U13/U15 +270 deg.
- Every non-zero rotation correction is externally backed: six packages
(SOT-23, SOIC-8, SOIC-8-1EP, QFN-24-1EP, CP_Elec_6.3x7.7, Arduino_UNO_R3)
are byte-identical to the v3 CPL that JLC built; the other four (LQFP-48,
SOIC-16, SOIC-16W, TSSOP-28) match KiBot's published JLCPCB rotation
table. KiBot's generic ^QFN- rule says 270 where the toolkit applied +90
to U6 - v3 hardware settles it in the toolkit's favour.
- Positions: 22 rows carry an AUTO TRANSLATE offset. 19 of 22 identical to
the v3 export, 20 of 22 equal the pad bounding-box centroid to 0.02 mm.
J10 is the only machine-placed part with a translation and it matches the
centroid exactly.
- Gerbers: 4 copper layers populated, both mask, both silk, F.Paste 40
apertures. B_Paste empty is correct (the one bottom-side part has no
paste). 523 PTH holes 0.30-1.63 mm, 6 NPTH at 3.20/3.25 mm.
Open before ordering: J10 (C12074 HR911105A) is the only through-hole part
carrying an LCSC number, so JLC's standard SMT line will not place it.
Also gitignore **/_to_delete/ (scratch folder for manual deletion).
Co-Authored-By: Claude <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
The .kicad_dru held one unconditional (min 0.15mm). A custom rule outranks
the netclass table and an unconditional rule matches every pair on the board,
so it was silently overriding the HV24 netclass's 0.5 mm everywhere: the
netclass said 0.5, DRC only ever enforced 0.15.
Rule file, three mutually-exclusive rules so order and specificity agree:
1. neither item HV24 -> 0.15 mm (unchanged)
2. either item HV24 -> 0.50 mm
3. except U2 pad-to-pad (its own land pattern)-> 0.15 mm
Rule 3 covers exactly one pair: U2 (MP1584EN, SOIC-8-EP) pad 7 (24V) to pad 9
(exposed thermal pad, GND) at 0.355 mm. That is the manufacturer's qualified
land pattern, set by the package and not by routing. U2's courtyard contains
9 pads and all 9 belong to U2, so the condition cannot match foreign copper;
the 24 foreign tracks/vias crossing that courtyard are excluded by the
A.Type == 'Pad' test and stay at the full 0.5 mm.
Copper: 13 of the 14 HV24-to-foreign gaps under 0.5 mm were routing, and all
13 are fixed. No component was moved or rotated.
3 width reductions (a narrower track can never reduce a clearance):
479e5357 24V -> U2.7 1.0 -> 0.6 U2's pads are 0.6 tall, so the
pad was already the bottleneck
854214dc FREQ_FAN -> U2.6 1.0 -> 0.6 1.14 mm long, R~0.93 mohm,
~8 mV at 3 A; IPC-2221 gives
~1.9 A at 10 C rise for 0.6 mm
30ed4012 24V -> DzG1.3 1.5 -> 0.8 leaf branch into a BZX84C15
SOT-23 clamp, sub-mA
5 track-vertex moves (never a via centre, never a pad centre):
/3V3_MODEM x3 corridor walks 0.55 mm east off the 24V bus
/USB_CC2 x2 opposite ends of one 6.05 mm segment pivot apart, opening
pad Rrp1.1 and the GND via at the same time
Verification (shapely geometry over every pad/via/track, diffed against the
unedited baseline so nothing pre-existing is miscounted as new):
HV24 inter-item pairs under 0.5 mm 13 -> 0
cross-footprint pairs under 0.15 mm 0 (unchanged)
pairs this edit created 0 at 0.15, 0 at 0.30, 0 at 0.50
per-net connectivity 180/180 nets whole, 0 orphan copper clusters
static DRC 0 violations, byte-identical to the C13 run
fab sweep 0 findings (edge clearance, drills, annular rings, outline)
thinnest new margin 0.5650 mm (pad Rrp1.1 <-> trk 1fed5fbb), looser than
five pre-existing HV24 pairs on this board
/24V_IN and IGN_IN copper byte-identical; 24V differs only in two width tokens
Pour reflow: the 0.5 mm rule widens the zone pullback around HV24 from 0.3 to
0.5 mm. Simulated the refill on all four pours at both values — the anchor
partition is identical (F.Cu 547 anchors / 35 groups, B.Cu 222/2, In1 33/5,
In2 220/7), so pressing B strands nothing. Area loss 115 mm2 on F.Cu, 4.6 mm2
on each of the other three.
Press B to refill zones before running DRC.
Leo's post-C12 DRC run left exactly one error:
[unconnected_items] Zone 'GND_POUR_FCU' [GND] on F.Cu <-> Zone 'GND_POUR_FCU' [GND] on F.Cu
KiCad prints only the zone anchor (60.1917, 40.3231) for both endpoints, so the
report cannot localise the stranded island. Located it analytically instead.
Root cause: U11 pad 9 [GND] @ (91.1275, 55.7600). It is the only GND item on the
board whose item-only connectivity cluster never reaches the In2.Cu GND plane
(two independent fill-independent proofs agree: layer-reach and In2-anchor). An
island survives KiCad's isolated-island removal only if some item props it up,
so pad 9 was propping up a GND_POUR_FCU island that touches nothing else.
island_removal_mode cannot fix that - it needs copper.
Pad 9 is fenced on all four sides (LQFP-48 lead ring, pad 8's westward /3V3_ETH
escape, pad 10's eastward /ETH_RSET escape, the /ETH_RXP chain under the body).
A 0.05mm grid router reached only 227 of 20883 legal cells and found no way to
touch existing GND copper without a via, so a through via is mandatory. A
0.005mm sweep of every legal via site in that pocket picked the best one on the
board's existing drill inventory - no third drill size added.
+ F.Cu GND track w0.3 (91.1275,55.7600) -> (90.1000,55.7600) -> (89.9950,55.8900)
+ F.Cu-B.Cu GND via 0.6/0.3 @ (89.9950,55.8900)
* U11 pad 9 -> (zone_connect 2)
Both track legs hold +0.2000mm clearance - the structural ceiling for a 0.3mm
track between 0.3mm leads on 0.5mm pitch. The via holds +0.1758mm copper and
+2.9705mm hole. The site sits inside GND_POUR_FCU, GND_POUR_BCU, P3V3_PLANE_IN1
and GND_PLANE_IN2 and outside MAGJACK_NO_POUR, with the nearest In2 signal
copper 1.10mm away, so the barrel lands on solid In2 GND plane.
zone_connect 2 mirrors the landed C12 treatment of pad 29: pads 8 and 10 each
knock 0.5mm of pour out around themselves, covering the whole pad-9 lane
(0.10mm tall < min_thickness 0.25), so the pour cannot reach pad 9 in any
connect mode. Solid mode removes the pad from the minimum-spoke test rather
than leaving a starved thermal behind.
Verified on the output file:
drc_c12.py 0 hard clearance violations, same 49 sub-epsilon marginals as C12
proof_c13.py 0 GND clusters without an In2 GND-plane anchor (was 1)
fcu_only.py 0 F.Cu-only GND clusters (was 1 = pad 9)
24V / /24V_IN / IGN_IN copper byte-identical (45 segments)
segments 1984->1986 vias 351->352 zones 5->5 footprints 189->189
Backup: .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C13 (md5 042efd5d)
Pushed: md5 94d36711d60985eef109913fcee36b09, 3502885 bytes
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
The .lck files are per-session editor locks picked up by an auto-sync commit;
they should never be versioned. v4-drc.rpt is Leo's KiCad 10 DRC run that C12
was built against (84 raw / 83 unique, 7 errors) - kept as the before-record.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
E1 clearance 0.1433 < 0.15 (/LED_A via vs /I2C_SCL via, 4 raw reports)
Relocated the /LED_A via 202c8cb4 from (147.15,85.85) to (147.25,86.22),
dead centre of the U13.1/U13.2 gap. uuid preserved; both attached segment
endpoints carried (In1.Cu 375e8fa7, B.Cu dee4fa4e). Worst gap now +0.2405.
E2 unconnected_items x2 + starved_thermal x1 -- ONE root cause.
The F.Cu GND pour pocket around U11 pad 29 was an island: it touched the
pad with a single thermal spoke but was fenced in by the LQFP-48 lead ring
and the escape routing, so it reached nothing else. Gave pad 29 a real
copper escape west to a new GND via that punches through to the In2 GND
plane, and set the pad to solid zone connection so the 2-spoke thermal
rule stops applying to a pad the pour can only reach from one side.
seg F.Cu w0.3 GND (99.4525,55.26)->(98.65,55.26) margin +0.2000
seg F.Cu w0.3 GND (98.65,55.26)->(97.55,54.45) margin +0.2000
via 0.6/0.3 F.Cu-B.Cu GND @(97.55,54.45) copper +0.2718
U11 pad 29 -> (zone_connect 2)
+0.2000 is the structural ceiling for a 0.5mm-pitch lead escape with a
0.3 track, and matches the neighbouring /3V3_ETH and /ETH_XI escapes.
E3 via_dangling /3V3_ETH via 3b0bb378 @(87.18,55.23) connected on F.Cu only.
Deleted. Touch test: 4 touching F.Cu segments, zero on In1/In2/B.Cu. The
F.Cu run at x=87.18 is collinear and continuous without it.
Verified: static DRC 0 hard violations (49 pre-existing marginals inside
KiCad's 0.0005 epsilon, unchanged). Per-net islands unchanged at 1 for
/LED_A /3V3_ETH /I2C_SCL /ETH_XI /ETH_RSET. New via lands inside
GND_PLANE_IN2 + GND_POUR_BCU, outside MAGJACK_NO_POUR. U11 is a plain
LQFP-48 with no exposed pad, so the under-body via is clear. Leo's 24V-class
copper (24V /24V_IN IGN_IN, 45 segments) byte-identical.
Backup: .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C12 (md5 7c2202cb)
New: md5 042efd5dd0cf99fdcfd27974b7bcb3c1 3502425 bytes
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Static-DRC battery (true pad geometry: circle/oval/roundrect/rect, NPTH as
hole-only) over 693 pads / 351 vias / 1982 segments -> 0 violations at the
project rule of 0.15mm min clearance, 0.25mm hole-to-hole.
Fixed:
[1] hole-to-hole -0.300 duplicate GND stitching via coincident at
(94.79,60.30) -- JLCPCB would have drilled the same hole twice. Removed.
[2] U11.13 (NC) +0.100 GND pad14 stub zigzag -> one straight lane x93.01
[3] U13.3 (GND) +0.130 I2C_SCL y=87.6 excursion -> single lane y=87.5277;
the GND stitcher the zigzag was dodging moved 0.138 north onto U13.2
pad copper (same uuid/net, still bonded to its track)
[4] ETH_LINKLED +0.130 3V3_ETH under-body via/rung -> y=57.455, the exact
centre of the only legal B.Cu window (RSET@56.89 / LINKLED@58.07);
165000nm both ways
[5] U11.17 +0.140 GND pad16 lane x94.14/94.15 -> single lane x94.10
[6][7] U11.46/47 +0.150 ETH_PMODE north lane y=49.31 -> 49.24
[8] stranded 1.5x1.5mm rule area (tracks/vias/pour not_allowed) nested in
U3's footprint but stranded ~22mm east of it with zero copper within
3mm -- a phantom no-route trap. Removed.
[9] stranded /3V3_ETH web on In2.Cu (the GND inner plane): orphaned remains
of the pad17 via removed in C10e, connected to nothing, punching a
clearance void in the GND plane. Removed.
Verified: paren balance 0; 188/188 footprints intact (only U3 shrinks, by the
nested rule area); top-level block census unchanged but segment 1992->1982 and
via 352->351; every touched net resolves to exactly ONE copper island
(/3V3_ETH went 2 -> 1); 24V-class hand-routed copper byte-identical
(24V 23 segs, /24V_IN 12 segs, IGN_IN 10 segs).
Pre-C11 board preserved at .mcp-backups/hbox-watchdog-v4.kicad_pcb.pre-C11
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- 54 of 90 free GND stitching vias aligned into rows/columns (axis equalize +
even spacing, move cap 2.0mm, largest 1.3mm); 8 track-connected free vias frozen
- every move clearance-validated (>=0.15mm to other-net copper, keepout excluded)
- +1 GND via at (92.25,59.8): W5500 AGND cluster (C93/C94/U11.14/16) was
pour-served only — now hard-bonded to the In2 plane
- silkscreen re-audit under new via field: 164 refs re-derived by the uniform
0.15mm-gap rule, 8 re-placed, 0 left unplaced
- verify: census 0 open nets, clearance-lite 0 hits <0.125mm
- NOTE: zone fills stale around moved vias — refill (B) in pcbnew
- C3: 22 detected component lines evened (edge-gap distribution between line
endpoints), 58 parts nudged; everything touched by the hand-routed 24V/IGN
tracks frozen (P1,Q10,D10,DzG1,C10,C11,C22,Rig1,Ren1,U2)
- C4: finer pass — pairs included (33 lines total, 17 more parts), 8 R/C
rotations normalized 180->0 / 270->90 (unpolarized only, pad angles kept
consistent), TOL 1.0mm
- IGN divider: Rigb1 10k -> 3.3k in sch+board (24V ign -> 3.13V at PA5, FT-pin
safe incl. 35V transients; was 7.5V, out of spec). Fleet rework note: same
swap recommended on the 10 EinarBoard 1.0 units
- Leo's 46 track segments byte-identical through both passes; 0 courtyard
conflicts; parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- Column A (R94,R95,C97,C98,C95): x=83.9, even pitch 3.575 (y 54.2-68.5)
- Column B (R92,C92,C93,C94,R96): x=87.5, even pitch 3.175 (y 50.3-63.0;
top pulled below MH1 which R92 would have hit at Leo's y46.4)
- C102/C90/C91 row: even x pitch (92.2 / 95.85 / 99.5 at y63.9)
- Serial column (C82,C83,R82,JP5): x=72.5, even pitch 4.4; Y2 centered on
the U10/U15 column (x=72); C85-C87 even pitch 2.4
- C96 kept at Leo's spot (Y1-centerline slot blocked by Y1/Rig1 courtyards)
- Verified: 0 pairwise courtyard conflicts
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- All footprint origins snapped to 0.1mm; 37 near-aligned row/column members
equalized (same-prefix groups within 0.35mm)
- ALL tracks erased for the clean re-route: 1100 segments + 237 vias removed;
zones kept (GND pour definitions + MAGJACK_NO_POUR rule area)
- Verified on Leo's B6 placement: 0 courtyard conflicts, nothing outside the
outline, parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- MOD1 shifted +25mm east of B4: its silkscreen outline (module body incl.
USB/SMA overhangs, 24.16mm west of the pad hull) now lands 0.8mm inside the
left board edge — connectors overhang the front as intended; pad hull
x85.5-131.8. U10 no longer displaced (module clears its Phase B spot)
- SW4G1 (4G NTRIP reset) moved beside the XBee sockets J7/J8 at (188,98.8),
2 stale stubs ripped; frees the bottom-edge strip x143-153
- P15/P16 dropped 0.7mm (origin y133.1) so their bodies clear the module's
bottom pad row; entry faces overhang the edge 1.3mm
- C103 clear of the module top pad row at (88,75.4)
- Verified: 0 pairwise courtyard conflicts; module's 32 pad holes clear of
all courtyards/pads; silk min-x 61.03 vs edge 60.19
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
J1/J2 are the STM32 Blackpill sockets, not the GNSS module; B2/B3 moved the
wrong part. This rebuilds from the Phase B baseline (0af0373):
- Blackpill J1/J2 back at original position/rotation with v3 routing intact
- MOD1 (ArduSimple simpleRTK2B Pro, the 10/8/6/8 socket pattern) moved 44.8mm
left: hull now x60.5-106.8, west edge 0.3mm from the board edge; 18 stale
pad stubs ripped for re-route
- P15/P16 into the bottom-edge window MOD1 vacated; U10 tucked between the
module rows (1.2mm TSSOP under ~8.5mm standoff); C103 clear of the top row
- ANT_CORRIDOR keepout retired (module owns the front-left; antenna exits there)
- 3D model vars repointed KICAD6/7 -> KICAD10 (58 refs)
- Verified: 0 pairwise courtyard conflicts; MOD1's 32 pad holes individually
checked clear of all courtyards and pads
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- J1/J2 rotated to vertical rows: J2 (outer) x63.77, J1 (inner) x78.77,
y52.8-101.1 — module hugs the front edge full-length, USB end (J1 pad20
/SYS5V) at the top-front corner; antenna exits directly at the front
- Front edge cleared: P15 (RS-485) -> top edge between MH5/MH1, P16 (RS-232)
-> bottom edge west of the modem pad row, H4 TTL -> top strip next to P5
- RJ45 kept at the bottom-left of the front edge (no other edge window fits
a 19x22.3mm magjack) with the no-pour zone moved under it
- Serial cluster re-laid east of the module; W5500 satellites auto-placed
by greedy collision-free placer; 0 pairwise courtyard conflicts (190 fp)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- J1/J2 socket pair translated -43.43mm: rows now x62.0-113.8, USB end
(J1 pad20 /SYS5V) at the left board edge; 49 stale J1/J2 pad stubs ripped
- Ethernet corner rebuilt lower-left: RJ45 J10 on left edge y106-125 inside
relocated MAGJACK_NO_POUR zone, W5500+25MHz+terminations below the serial
stack, clear of the existing R5/R6/R7/D1/C5/C7 LED cluster
- ANT_CORRIDOR_KEEPOUT retired (antenna now exits at the module end itself)
- Rig1 nudged below Rigb1 (was inside J2's new courtyard band), stub ripped
- 3D models: 58 legacy KICAD6/KICAD7 3DMODEL_DIR refs repointed at
KICAD10_3DMODEL_DIR so new parts render in the 3D viewer
- Verified: 190 footprints, 0 pairwise courtyard conflicts, parens balanced
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
- Outline left edge 80.19->60.19; MH5/MH6 mounting holes cloned to new corners
- Antenna corridor keepout front-left (notched around MH6) + magjack no-pour/no-via zone
- RJ45 J10 + RS-485 P15 + RS-232 P16 on new left edge behind antenna corridor
- W5500 U11 + 25MHz + terminations between jack and P5; 3V3_ETH buck U12/L8/D11
in the freed P13/H3 gap under the module (low-profile), bulk caps at load
- SC16IS752 U10 serial cluster behind P15/P16; MAX3232 U15, SP3485 U14
- PCF8574 U13 clear of MOD1 pad ring; RGB JST P14 on right edge (freed P3 slot)
- H4 TTL header moved to front edge (was under module, on D5)
- 24V entry block relocated beside P1 (Q10/C10 in P12 lane, D10/DzG1/Rrp1 pocket);
old cross-board 24V routing ripped for HV24 re-route
- P3/P13/H3 depopulated; J1/J2/DB pad nets updated (ETH SPI, SER_IRQ, LED flip)
- Fix Phase A miss: SC16IS752 pins 13/14 (I2C SCL/SDA) now wired in sch + board
- Placement verified: 190 footprints, 0 courtyard conflicts, 0 corridor intrusions,
all new nets 2-ended (verify_phase_b.py)
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
v4 = the live 1.1/Phase-A design (J1 renumbered, blocks M/N/O, HV24, PFI 4.40V). v3-PROD trio = exact as-fabbed state from 9892279 (mirrored J1 as the bench/fleet boards physically are) - do not edit. dru/prl carried to v4. Off-grid warning backlog stays visible-but-muted; real geometry sweep slated for Phase D.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Root cause of 23 ERC errors: vertically-stacked 2-pin parts closer than 15.24mm shared stub columns -> KiCad merged collinear overlapping stubs -> orphaned pins + fused nets (C85-C89 chain shorted C1N/C2P/VP/VN/GND/3V3; RGB chain fused). Regenerated from pre-Phase-A base with grid-snapped origins, one x-column per part, geometry auditor (collinear overlap + T-touch + label-anchor collision checks) now part of the generator. P13 depop made surgical (R61 FB wire preserved). PF10/PF11 added. rjmap LED/TCT nets direct (no alias bridges). Netclass patterns re-applied onto KiCad-canonical pro; note: pro file is vulnerable to open-KiCad resave clobber.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
Keystone: gauge moves to PCF8574 on I2C1 -> frees SPI2 for W5500; SC16IS752 dual-UART bridge on I2C gives RS-485 (Modbus RTU) + RS-232/TTL with zero MCU pins. New 3V3_ETH rail from SYS5V (survives stack power-cycles). Carry-over errata state + depop list + phases A-E.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
J1 pads renumbered end-for-end (positions/uuids kept, nets follow numbers, lib id renamed Drogheda:..._RevNum_EJ1 so library-update cannot revert); verified pad-by-pad against the module landing map. R51 287k->270k on board+schematic (PFI trip 4.60->4.40V falling, per 24-Jul bench data). HV24 class (0.5mm clearance) assigned to /24V_IN, 24V, IGN_IN, Q10_GATE after the 23-Jul inner-layer bridge incident. 177 segments/vias ripped on the 11 J1 signal nets + 5 power stubs: reroute pending in the inter-socket channel. NOTE: pre-existing PWR_HI/PWR_MID netclass patterns lack the '/' prefix and likely never matched.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01GSKKes8GsS4YHAMWJ44tCm
